From patchwork Wed Mar 11 02:53:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhenyu Ye X-Patchwork-Id: 11430599 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 458CB1874 for ; Wed, 11 Mar 2020 02:56:36 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 1BDA1222C3 for ; Wed, 11 Mar 2020 02:56:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1BDA1222C3 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id 593546B0008; Tue, 10 Mar 2020 22:56:34 -0400 (EDT) Delivered-To: linux-mm-outgoing@kvack.org Received: by kanga.kvack.org (Postfix, from userid 40) id 4CEAF6B000A; Tue, 10 Mar 2020 22:56:34 -0400 (EDT) X-Original-To: int-list-linux-mm@kvack.org X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 36C756B000C; Tue, 10 Mar 2020 22:56:34 -0400 (EDT) X-Original-To: linux-mm@kvack.org X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0042.hostedemail.com [216.40.44.42]) by kanga.kvack.org (Postfix) with ESMTP id 163806B0008 for ; Tue, 10 Mar 2020 22:56:34 -0400 (EDT) Received: from smtpin30.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay03.hostedemail.com (Postfix) with ESMTP id E0ED68248047 for ; Wed, 11 Mar 2020 02:56:33 +0000 (UTC) X-FDA: 76581568266.30.value25_39417b1f2e51c X-Spam-Summary: 1,0,0,,d41d8cd98f00b204,yezhenyu2@huawei.com,,RULES_HIT:30054:30080,0,RBL:45.249.212.190:@huawei.com:.lbl8.mailshell.net-62.18.2.100 64.95.201.95,CacheIP:none,Bayesian:0.5,0.5,0.5,Netcheck:none,DomainCache:0,MSF:not bulk,SPF:fp,MSBL:0,DNSBL:neutral,Custom_rules:0:0:0,LFtime:22,LUA_SUMMARY:none X-HE-Tag: value25_39417b1f2e51c X-Filterd-Recvd-Size: 4251 Received: from huawei.com (szxga04-in.huawei.com [45.249.212.190]) by imf08.hostedemail.com (Postfix) with ESMTP for ; Wed, 11 Mar 2020 02:56:33 +0000 (UTC) Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id CE3F0E0F8BC4C2687253; Wed, 11 Mar 2020 10:56:23 +0800 (CST) Received: from DESKTOP-KKJBAGG.china.huawei.com (10.173.220.25) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Wed, 11 Mar 2020 10:56:16 +0800 From: Zhenyu Ye To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v1 2/3] arm64: tlb: use mm_struct.context.flags to indicate TTL Date: Wed, 11 Mar 2020 10:53:08 +0800 Message-ID: <20200311025309.1743-3-yezhenyu2@huawei.com> X-Mailer: git-send-email 2.22.0.windows.1 In-Reply-To: <20200311025309.1743-1-yezhenyu2@huawei.com> References: <20200311025309.1743-1-yezhenyu2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.173.220.25] X-CFilter-Loop: Reflected X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Use Architecture-specific MM context to indicate the level of page table walk. This avoids lots of changes to common-interface. Signed-off-by: Zhenyu Ye --- arch/arm64/include/asm/mmu.h | 11 +++++++++++ arch/arm64/include/asm/tlbflush.h | 8 +++++--- 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h index e4d862420bb4..7410d2997c2a 100644 --- a/arch/arm64/include/asm/mmu.h +++ b/arch/arm64/include/asm/mmu.h @@ -8,6 +8,10 @@ #include #define MMCF_AARCH32 0x1 /* mm context flag for AArch32 executables */ +#define TLBI_LEVEL_1 0x10 /* mm context flag for the level of ptw */ +#define TLBI_LEVEL_2 0x20 +#define TLBI_LEVEL_3 0x30 + #define USER_ASID_BIT 48 #define USER_ASID_FLAG (UL(1) << USER_ASID_BIT) #define TTBR_ASID_MASK (UL(0xffff) << 48) @@ -19,6 +23,10 @@ typedef struct { atomic64_t id; void *vdso; + /* + * flags[3:0]: AArch32 executables + * flags[7:4]: the level of page table walk + */ unsigned long flags; } mm_context_t; @@ -29,6 +37,9 @@ typedef struct { */ #define ASID(mm) ((mm)->context.id.counter & 0xffff) +/* This macro is only used by TLBI TTL */ +#define TLBI_LEVEL(mm) ((mm)->context.flags >> 4 & 0xf) + extern bool arm64_use_ng_mappings; static inline bool arm64_kernel_unmapped_at_el0(void) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index 10b12710b7cc..9f02a5383ac3 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -172,7 +172,8 @@ static inline void flush_tlb_mm(struct mm_struct *mm) static inline void flush_tlb_page_nosync(struct vm_area_struct *vma, unsigned long uaddr) { - unsigned long addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm), 0); + unsigned long ttl = (__TLB_TG << 2) + TLBI_LEVEL(vma->vm_mm); + unsigned long addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm), ttl); dsb(ishst); __tlbi(vale1is, addr); @@ -197,6 +198,7 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, unsigned long stride, bool last_level) { unsigned long asid = ASID(vma->vm_mm); + unsigned long ttl = (__TLB_TG << 2) + TLBI_LEVEL(vma->vm_mm); unsigned long addr; start = round_down(start, stride); @@ -210,8 +212,8 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, /* Convert the stride into units of 4k */ stride >>= 12; - start = __TLBI_VADDR(start, asid, 0); - end = __TLBI_VADDR(end, asid, 0); + start = __TLBI_VADDR(start, asid, ttl); + end = __TLBI_VADDR(end, asid, ttl); dsb(ishst); for (addr = start; addr < end; addr += stride) {