diff mbox series

[v1,1/6] arm64: Detect the ARMv8.4 TTL feature

Message ID 20200403090048.938-2-yezhenyu2@huawei.com (mailing list archive)
State New, archived
Headers show
Series arm64: tlb: add support for TTL feature | expand

Commit Message

Zhenyu Ye April 3, 2020, 9 a.m. UTC 
From: Marc Zyngier <maz@kernel.org>

In order to reduce the cost of TLB invalidation, the ARMv8.4 TTL
feature allows TLBs to be issued with a level allowing for quicker
invalidation.

Let's detect the feature for now. Further patches will implement
its actual usage.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
---
 arch/arm64/include/asm/cpucaps.h |  3 ++-
 arch/arm64/include/asm/sysreg.h  |  1 +
 arch/arm64/kernel/cpufeature.c   | 11 +++++++++++
 3 files changed, 14 insertions(+), 1 deletion(-)

Comments

Christoph Hellwig April 21, 2020, 4:53 p.m. UTC | #1 
On Fri, Apr 03, 2020 at 05:00:43PM +0800, Zhenyu Ye wrote:
> From: Marc Zyngier <maz@kernel.org>
> 
> In order to reduce the cost of TLB invalidation, the ARMv8.4 TTL
> feature allows TLBs to be issued with a level allowing for quicker
> invalidation.

What does "issued with a level" mean?
Peter Zijlstra April 21, 2020, 5:13 p.m. UTC | #2 
On Tue, Apr 21, 2020 at 09:53:46AM -0700, Christoph Hellwig wrote:
> On Fri, Apr 03, 2020 at 05:00:43PM +0800, Zhenyu Ye wrote:
> > From: Marc Zyngier <maz@kernel.org>
> > 
> > In order to reduce the cost of TLB invalidation, the ARMv8.4 TTL
> > feature allows TLBs to be issued with a level allowing for quicker
> > invalidation.
> 
> What does "issued with a level" mean?

What I understood it to be is page-size based on page-table hierarchy.
Just like we have on x86, 4k, 2m, 1g etc..

So where x86 INVLPG will tear down any sized page for the address given,
you can now day, kill me the PMD level translation for @addr.

Power9 radix also has things like this.
Christoph Hellwig April 21, 2020, 5:16 p.m. UTC | #3 
On Tue, Apr 21, 2020 at 07:13:28PM +0200, Peter Zijlstra wrote:
> On Tue, Apr 21, 2020 at 09:53:46AM -0700, Christoph Hellwig wrote:
> > On Fri, Apr 03, 2020 at 05:00:43PM +0800, Zhenyu Ye wrote:
> > > From: Marc Zyngier <maz@kernel.org>
> > > 
> > > In order to reduce the cost of TLB invalidation, the ARMv8.4 TTL
> > > feature allows TLBs to be issued with a level allowing for quicker
> > > invalidation.
> > 
> > What does "issued with a level" mean?
> 
> What I understood it to be is page-size based on page-table hierarchy.
> Just like we have on x86, 4k, 2m, 1g etc..
> 
> So where x86 INVLPG will tear down any sized page for the address given,
> you can now day, kill me the PMD level translation for @addr.
> 
> Power9 radix also has things like this.

Maybe this needs to be spelled out a little more?  The current commit
log sounds like paper generated by a neural network.
Zhenyu Ye April 22, 2020, 2:13 a.m. UTC | #4 
On 2020/4/22 1:16, Christoph Hellwig wrote:
> On Tue, Apr 21, 2020 at 07:13:28PM +0200, Peter Zijlstra wrote:
>> On Tue, Apr 21, 2020 at 09:53:46AM -0700, Christoph Hellwig wrote:
>>> On Fri, Apr 03, 2020 at 05:00:43PM +0800, Zhenyu Ye wrote:
>>>> From: Marc Zyngier <maz@kernel.org>
>>>>
>>>> In order to reduce the cost of TLB invalidation, the ARMv8.4 TTL
>>>> feature allows TLBs to be issued with a level allowing for quicker
>>>> invalidation.
>>>
>>> What does "issued with a level" mean?
>>
>> What I understood it to be is page-size based on page-table hierarchy.
>> Just like we have on x86, 4k, 2m, 1g etc..
>>
>> So where x86 INVLPG will tear down any sized page for the address given,
>> you can now day, kill me the PMD level translation for @addr.
>>
>> Power9 radix also has things like this.
> 
> Maybe this needs to be spelled out a little more?  The current commit
> log sounds like paper generated by a neural network.
>

Emm... This patch was synchronized from Marc's NV series [1].
"issued with a level" means the TLBs now can get which levels of
page tables the @addr is in. You can also understand it as
page-size as Peter said above, just like pud, pmd, pte...

Anyway, I will explain this in more detail.

Thanks,
Zhenyu
diff mbox series

Patch

diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
index 865e0253fc1e..8b3b4dd612b3 100644
--- a/arch/arm64/include/asm/cpucaps.h
+++ b/arch/arm64/include/asm/cpucaps.h
@@ -58,7 +58,8 @@ 
 #define ARM64_WORKAROUND_SPECULATIVE_AT_NVHE	48
 #define ARM64_HAS_E0PD				49
 #define ARM64_HAS_RNG				50
+#define ARM64_HAS_ARMv8_4_TTL			51
 
-#define ARM64_NCAPS				51
+#define ARM64_NCAPS				52
 
 #endif /* __ASM_CPUCAPS_H */
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index b91570ff9db1..a28b76f32ba7 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -685,6 +685,7 @@ 
 
 /* id_aa64mmfr2 */
 #define ID_AA64MMFR2_E0PD_SHIFT		60
+#define ID_AA64MMFR2_TTL_SHIFT		48
 #define ID_AA64MMFR2_FWB_SHIFT		40
 #define ID_AA64MMFR2_AT_SHIFT		32
 #define ID_AA64MMFR2_LVA_SHIFT		16
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 0b6715625cf6..cbe46ad2900a 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -241,6 +241,7 @@  static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 
 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
@@ -1523,6 +1524,16 @@  static const struct arm64_cpu_capabilities arm64_features[] = {
 		.matches = has_cpuid_feature,
 		.cpu_enable = cpu_has_fwb,
 	},
+	{
+		.desc = "ARMv8.4 Translation Table Level",
+		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
+		.capability = ARM64_HAS_ARMv8_4_TTL,
+		.sys_reg = SYS_ID_AA64MMFR2_EL1,
+		.sign = FTR_UNSIGNED,
+		.field_pos = ID_AA64MMFR2_TTL_SHIFT,
+		.min_field_value = 1,
+		.matches = has_cpuid_feature,
+	},
 #ifdef CONFIG_ARM64_HW_AFDBM
 	{
 		/*