diff mbox series

[v1] arm64: tlb: don't set the ttl value in flush_tlb_page_nosync

Message ID 20200710094158.468-1-yezhenyu2@huawei.com (mailing list archive)
State New, archived
Headers show
Series [v1] arm64: tlb: don't set the ttl value in flush_tlb_page_nosync | expand

Commit Message

Zhenyu Ye July 10, 2020, 9:41 a.m. UTC
flush_tlb_page_nosync() may be called from pmd level, so we
can not set the ttl = 3 here.

The callstack is as follows:

	pmdp_set_access_flags
		ptep_set_access_flags
			flush_tlb_fix_spurious_fault
				flush_tlb_page
					flush_tlb_page_nosync

Reported-by: Catalin Marinas <catalin.marinas@arm.com>
Fixes: e735b98a5fe0 ("arm64: Add tlbi_user_level TLB invalidation helper")
Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
---
 arch/arm64/include/asm/tlbflush.h | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

Comments

Catalin Marinas July 10, 2020, 3:29 p.m. UTC | #1
On Fri, 10 Jul 2020 17:41:58 +0800, Zhenyu Ye wrote:
> flush_tlb_page_nosync() may be called from pmd level, so we
> can not set the ttl = 3 here.
> 
> The callstack is as follows:
> 
> 	pmdp_set_access_flags
> 		ptep_set_access_flags
> 			flush_tlb_fix_spurious_fault
> 				flush_tlb_page
> 					flush_tlb_page_nosync

Applied to arm64 (for-next/tlbi), thanks!

[1/1] arm64: tlb: don't set the ttl value in flush_tlb_page_nosync
      https://git.kernel.org/arm64/c/61c11656b67b
diff mbox series

Patch

diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index edfec8139ef8..7528c84a94ef 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -252,9 +252,8 @@  static inline void flush_tlb_page_nosync(struct vm_area_struct *vma,
 	unsigned long addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm));
 
 	dsb(ishst);
-	/* This function is only called on a small page */
-	__tlbi_level(vale1is, addr, 3);
-	__tlbi_user_level(vale1is, addr, 3);
+	__tlbi(vale1is, addr);
+	__tlbi_user(vale1is, addr);
 }
 
 static inline void flush_tlb_page(struct vm_area_struct *vma,