From patchwork Fri Sep 25 14:57:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu-cheng Yu X-Patchwork-Id: 11800021 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6A19C92C for ; Fri, 25 Sep 2020 14:58:44 +0000 (UTC) Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by mail.kernel.org (Postfix) with ESMTP id 2E85120715 for ; Fri, 25 Sep 2020 14:58:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2E85120715 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=owner-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix) id A27A38E0003; Fri, 25 Sep 2020 10:58:18 -0400 (EDT) Delivered-To: linux-mm-outgoing@kvack.org Received: by kanga.kvack.org (Postfix, from userid 40) id 9D9208E0001; Fri, 25 Sep 2020 10:58:18 -0400 (EDT) X-Original-To: int-list-linux-mm@kvack.org X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 398106B00A4; Fri, 25 Sep 2020 10:58:18 -0400 (EDT) X-Original-To: linux-mm@kvack.org X-Delivered-To: linux-mm@kvack.org Received: from forelay.hostedemail.com (smtprelay0161.hostedemail.com [216.40.44.161]) by kanga.kvack.org (Postfix) with ESMTP id 1969A6B009F for ; Fri, 25 Sep 2020 10:58:18 -0400 (EDT) Received: from smtpin09.hostedemail.com (10.5.19.251.rfc1918.com [10.5.19.251]) by forelay02.hostedemail.com (Postfix) with ESMTP id CE58F4DA2 for ; Fri, 25 Sep 2020 14:58:17 +0000 (UTC) X-FDA: 77301889434.09.band26_471195527168 Received: from filter.hostedemail.com (10.5.16.251.rfc1918.com [10.5.16.251]) by smtpin09.hostedemail.com (Postfix) with ESMTP id AEA32180AD804 for ; Fri, 25 Sep 2020 14:58:17 +0000 (UTC) X-Spam-Summary: 1,0,0,,d41d8cd98f00b204,yu-cheng.yu@intel.com,,RULES_HIT:30045:30046:30051:30054:30055:30056:30064,0,RBL:134.134.136.100:@intel.com:.lbl8.mailshell.net-64.95.201.95 62.18.0.100;04y866cr33weyscmkhskjrpqhsxztyc4wstfs5c8stfi8s6a1upebddhy96h35d.stbjzzuk1wi4icjyw35fuea1mxjzu6rhch8n8tiuppkj7jg9ra8rabrosyoo9tz.q-lbl8.mailshell.net-223.238.255.100,CacheIP:none,Bayesian:0.5,0.5,0.5,Netcheck:none,DomainCache:0,MSF:not bulk,SPF:ft,MSBL:0,DNSBL:neutral,Custom_rules:0:0:0,LFtime:24,LUA_SUMMARY:none X-HE-Tag: band26_471195527168 X-Filterd-Recvd-Size: 5509 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by imf25.hostedemail.com (Postfix) with ESMTP for ; Fri, 25 Sep 2020 14:58:16 +0000 (UTC) IronPort-SDR: RKdaS379CS29rwwHejYojAdnhAU2V6uXKgFwV21wOFbTwkZNdjXxNhaOmGNV8gfFTOlHxA6K05 HA0xZ1piYyJA== X-IronPort-AV: E=McAfee;i="6000,8403,9755"; a="225704483" X-IronPort-AV: E=Sophos;i="5.77,302,1596524400"; d="scan'208";a="225704483" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Sep 2020 07:58:14 -0700 IronPort-SDR: vbxmrk/2vgkev8nhj22uATZJCJ9qznrWAemWkziCn88O1cAblaFXd96zFg0I479YiFlk0lqMM/ L1FR1R7AxAyQ== X-IronPort-AV: E=Sophos;i="5.77,302,1596524400"; d="scan'208";a="512916965" Received: from yyu32-desk.sc.intel.com ([143.183.136.146]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Sep 2020 07:58:13 -0700 From: Yu-cheng Yu To: x86@kernel.org, "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H.J. Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , "Ravi V. Shankar" , Vedvyas Shanbhogue , Dave Martin , Weijiang Yang , Pengfei Xu Cc: Yu-cheng Yu Subject: [PATCH v13 3/8] x86/cet/ibt: Handle signals for Indirect Branch Tracking Date: Fri, 25 Sep 2020 07:57:59 -0700 Message-Id: <20200925145804.5821-4-yu-cheng.yu@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200925145804.5821-1-yu-cheng.yu@intel.com> References: <20200925145804.5821-1-yu-cheng.yu@intel.com> MIME-Version: 1.0 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: An indirect CALL/JMP moves the indirect branch tracking (IBT) state machine to WAIT_ENDBR status until the instruction reaches an ENDBR opcode. If the CALL/JMP does not reach an ENDBR opcode, the processor raises a control- protection fault. WAIT_ENDBR status can be read from MSR_IA32_U_CET. WAIT_ENDBR is cleared for signal handling, and restored for sigreturn. IBT state machine is described in Intel SDM Vol. 1, Sec. 18.3. Signed-off-by: Yu-cheng Yu --- v9: - Fix missing WAIT_ENDBR in signal handling. arch/x86/kernel/cet.c | 27 +++++++++++++++++++++++++-- arch/x86/kernel/fpu/signal.c | 8 +++++--- 2 files changed, 30 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cet.c b/arch/x86/kernel/cet.c index e95fadb264f7..1f8b72269166 100644 --- a/arch/x86/kernel/cet.c +++ b/arch/x86/kernel/cet.c @@ -295,6 +295,13 @@ void cet_restore_signal(struct sc_ext *sc_ext) msr_val |= CET_SHSTK_EN; } + if (cet->ibt_enabled) { + msr_val |= (CET_ENDBR_EN | CET_NO_TRACK_EN); + + if (sc_ext->wait_endbr) + msr_val |= CET_WAIT_ENDBR; + } + if (test_thread_flag(TIF_NEED_FPU_LOAD)) cet_user_state->user_cet = msr_val; else @@ -335,9 +342,25 @@ int cet_setup_signal(bool ia32, unsigned long rstor_addr, struct sc_ext *sc_ext) sc_ext->ssp = new_ssp; } - if (ssp) { + if (ssp || cet->ibt_enabled) { + start_update_msrs(); - wrmsrl(MSR_IA32_PL3_SSP, ssp); + + if (ssp) + wrmsrl(MSR_IA32_PL3_SSP, ssp); + + if (cet->ibt_enabled) { + u64 r; + + rdmsrl(MSR_IA32_U_CET, r); + + if (r & CET_WAIT_ENDBR) { + sc_ext->wait_endbr = 1; + r &= ~CET_WAIT_ENDBR; + wrmsrl(MSR_IA32_U_CET, r); + } + } + end_update_msrs(); } diff --git a/arch/x86/kernel/fpu/signal.c b/arch/x86/kernel/fpu/signal.c index c0c2141cb4b3..077853ef6f48 100644 --- a/arch/x86/kernel/fpu/signal.c +++ b/arch/x86/kernel/fpu/signal.c @@ -57,7 +57,8 @@ int save_cet_to_sigframe(int ia32, void __user *fp, unsigned long restorer) { int err = 0; - if (!current->thread.cet.shstk_size) + if (!current->thread.cet.shstk_size && + !current->thread.cet.ibt_enabled) return 0; if (fp) { @@ -89,7 +90,8 @@ static int get_cet_from_sigframe(int ia32, void __user *fp, struct sc_ext *ext) memset(ext, 0, sizeof(*ext)); - if (!current->thread.cet.shstk_size) + if (!current->thread.cet.shstk_size && + !current->thread.cet.ibt_enabled) return 0; if (fp) { @@ -577,7 +579,7 @@ static unsigned long fpu__alloc_sigcontext_ext(unsigned long sp) * sigcontext_ext is at: fpu + fpu_user_xstate_size + * FP_XSTATE_MAGIC2_SIZE, then aligned to 8. */ - if (cet->shstk_size) + if (cet->shstk_size || cet->ibt_enabled) sp -= (sizeof(struct sc_ext) + 8); return sp;