diff mbox series

[v14,02/26] x86/cpufeatures: Add CET CPU feature flags for Control-flow Enforcement Technology (CET)

Message ID 20201012153850.26996-3-yu-cheng.yu@intel.com (mailing list archive)
State New, archived
Headers show
Series Control-flow Enforcement: Shadow Stack | expand

Commit Message

Yu-cheng Yu Oct. 12, 2020, 3:38 p.m. UTC 
Add CPU feature flags for Control-flow Enforcement Technology (CET).

CPUID.(EAX=7,ECX=0):ECX[bit 7] Shadow stack
CPUID.(EAX=7,ECX=0):EDX[bit 20] Indirect Branch Tracking

Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
Reviewed-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Kees Cook <keescook@chromium.org>
---
 arch/x86/include/asm/cpufeatures.h       | 2 ++
 arch/x86/kernel/cpu/cpuid-deps.c         | 2 ++
 tools/arch/x86/include/asm/cpufeatures.h | 2 ++
 3 files changed, 6 insertions(+)

Comments

Borislav Petkov Nov. 6, 2020, 6:49 p.m. UTC | #1 
On Mon, Oct 12, 2020 at 08:38:26AM -0700, Yu-cheng Yu wrote:
> Add CPU feature flags for Control-flow Enforcement Technology (CET).
> 
> CPUID.(EAX=7,ECX=0):ECX[bit 7] Shadow stack
> CPUID.(EAX=7,ECX=0):EDX[bit 20] Indirect Branch Tracking
> 
> Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
> Reviewed-by: Borislav Petkov <bp@suse.de>

This is not the patch I reviewed, why do you keep my Reviewed-by tag?

> Reviewed-by: Kees Cook <keescook@chromium.org>
> ---
>  arch/x86/include/asm/cpufeatures.h       | 2 ++
>  arch/x86/kernel/cpu/cpuid-deps.c         | 2 ++
>  tools/arch/x86/include/asm/cpufeatures.h | 2 ++
>  3 files changed, 6 insertions(+)
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 2901d5df4366..c794e18e8a14 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -341,6 +341,7 @@
>  #define X86_FEATURE_OSPKE		(16*32+ 4) /* OS Protection Keys Enable */
>  #define X86_FEATURE_WAITPKG		(16*32+ 5) /* UMONITOR/UMWAIT/TPAUSE Instructions */
>  #define X86_FEATURE_AVX512_VBMI2	(16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
> +#define X86_FEATURE_SHSTK		(16*32+ 7) /* Shadow Stack */
>  #define X86_FEATURE_GFNI		(16*32+ 8) /* Galois Field New Instructions */
>  #define X86_FEATURE_VAES		(16*32+ 9) /* Vector AES */
>  #define X86_FEATURE_VPCLMULQDQ		(16*32+10) /* Carry-Less Multiplication Double Quadword */
> @@ -370,6 +371,7 @@
>  #define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */
>  #define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */
>  #define X86_FEATURE_ARCH_LBR		(18*32+19) /* Intel ARCH LBR */
> +#define X86_FEATURE_IBT			(18*32+20) /* Indirect Branch Tracking */
>  #define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */
>  #define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */
>  #define X86_FEATURE_FLUSH_L1D		(18*32+28) /* Flush L1D cache */
> diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c
> index 3cbe24ca80ab..fec83cc74b9e 100644
> --- a/arch/x86/kernel/cpu/cpuid-deps.c
> +++ b/arch/x86/kernel/cpu/cpuid-deps.c
> @@ -69,6 +69,8 @@ static const struct cpuid_dep cpuid_deps[] = {
>  	{ X86_FEATURE_CQM_MBM_TOTAL,		X86_FEATURE_CQM_LLC   },
>  	{ X86_FEATURE_CQM_MBM_LOCAL,		X86_FEATURE_CQM_LLC   },
>  	{ X86_FEATURE_AVX512_BF16,		X86_FEATURE_AVX512VL  },
> +	{ X86_FEATURE_SHSTK,			X86_FEATURE_XSAVES    },
> +	{ X86_FEATURE_IBT,			X86_FEATURE_XSAVES    },
>  	{}
>  };
>  
> diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
> index 2901d5df4366..c794e18e8a14 100644
> --- a/tools/arch/x86/include/asm/cpufeatures.h
> +++ b/tools/arch/x86/include/asm/cpufeatures.h
> @@ -341,6 +341,7 @@
>  #define X86_FEATURE_OSPKE		(16*32+ 4) /* OS Protection Keys Enable */
>  #define X86_FEATURE_WAITPKG		(16*32+ 5) /* UMONITOR/UMWAIT/TPAUSE Instructions */
>  #define X86_FEATURE_AVX512_VBMI2	(16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
> +#define X86_FEATURE_SHSTK		(16*32+ 7) /* Shadow Stack */
>  #define X86_FEATURE_GFNI		(16*32+ 8) /* Galois Field New Instructions */
>  #define X86_FEATURE_VAES		(16*32+ 9) /* Vector AES */
>  #define X86_FEATURE_VPCLMULQDQ		(16*32+10) /* Carry-Less Multiplication Double Quadword */
> @@ -370,6 +371,7 @@
>  #define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */
>  #define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */
>  #define X86_FEATURE_ARCH_LBR		(18*32+19) /* Intel ARCH LBR */
> +#define X86_FEATURE_IBT			(18*32+20) /* Indirect Branch Tracking */
>  #define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */
>  #define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */
>  #define X86_FEATURE_FLUSH_L1D		(18*32+28) /* Flush L1D cache */

We don't sync the respective change in tools/ - Arnaldo does.
Yu-cheng Yu Nov. 6, 2020, 7:48 p.m. UTC | #2 
On 11/6/2020 10:49 AM, Borislav Petkov wrote:
> On Mon, Oct 12, 2020 at 08:38:26AM -0700, Yu-cheng Yu wrote:
>> Add CPU feature flags for Control-flow Enforcement Technology (CET).
>>
>> CPUID.(EAX=7,ECX=0):ECX[bit 7] Shadow stack
>> CPUID.(EAX=7,ECX=0):EDX[bit 20] Indirect Branch Tracking
>>
>> Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
>> Reviewed-by: Borislav Petkov <bp@suse.de>
> 
> This is not the patch I reviewed, why do you keep my Reviewed-by tag?

I will drop it.  It has been re-based many times, and probably I 
accidentally introduced something else?

> 
>> Reviewed-by: Kees Cook <keescook@chromium.org>
>> ---
>>   arch/x86/include/asm/cpufeatures.h       | 2 ++
>>   arch/x86/kernel/cpu/cpuid-deps.c         | 2 ++
>>   tools/arch/x86/include/asm/cpufeatures.h | 2 ++
>>   3 files changed, 6 insertions(+)
>>
>> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
>> index 2901d5df4366..c794e18e8a14 100644
>> --- a/arch/x86/include/asm/cpufeatures.h
>> +++ b/arch/x86/include/asm/cpufeatures.h
>> @@ -341,6 +341,7 @@
>>   #define X86_FEATURE_OSPKE		(16*32+ 4) /* OS Protection Keys Enable */
>>   #define X86_FEATURE_WAITPKG		(16*32+ 5) /* UMONITOR/UMWAIT/TPAUSE Instructions */
>>   #define X86_FEATURE_AVX512_VBMI2	(16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
>> +#define X86_FEATURE_SHSTK		(16*32+ 7) /* Shadow Stack */
>>   #define X86_FEATURE_GFNI		(16*32+ 8) /* Galois Field New Instructions */
>>   #define X86_FEATURE_VAES		(16*32+ 9) /* Vector AES */
>>   #define X86_FEATURE_VPCLMULQDQ		(16*32+10) /* Carry-Less Multiplication Double Quadword */
>> @@ -370,6 +371,7 @@
>>   #define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */
>>   #define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */
>>   #define X86_FEATURE_ARCH_LBR		(18*32+19) /* Intel ARCH LBR */
>> +#define X86_FEATURE_IBT			(18*32+20) /* Indirect Branch Tracking */
>>   #define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */
>>   #define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */
>>   #define X86_FEATURE_FLUSH_L1D		(18*32+28) /* Flush L1D cache */
>> diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c
>> index 3cbe24ca80ab..fec83cc74b9e 100644
>> --- a/arch/x86/kernel/cpu/cpuid-deps.c
>> +++ b/arch/x86/kernel/cpu/cpuid-deps.c
>> @@ -69,6 +69,8 @@ static const struct cpuid_dep cpuid_deps[] = {
>>   	{ X86_FEATURE_CQM_MBM_TOTAL,		X86_FEATURE_CQM_LLC   },
>>   	{ X86_FEATURE_CQM_MBM_LOCAL,		X86_FEATURE_CQM_LLC   },
>>   	{ X86_FEATURE_AVX512_BF16,		X86_FEATURE_AVX512VL  },
>> +	{ X86_FEATURE_SHSTK,			X86_FEATURE_XSAVES    },
>> +	{ X86_FEATURE_IBT,			X86_FEATURE_XSAVES    },
>>   	{}
>>   };
>>   
>> diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
>> index 2901d5df4366..c794e18e8a14 100644
>> --- a/tools/arch/x86/include/asm/cpufeatures.h
>> +++ b/tools/arch/x86/include/asm/cpufeatures.h
>> @@ -341,6 +341,7 @@
>>   #define X86_FEATURE_OSPKE		(16*32+ 4) /* OS Protection Keys Enable */
>>   #define X86_FEATURE_WAITPKG		(16*32+ 5) /* UMONITOR/UMWAIT/TPAUSE Instructions */
>>   #define X86_FEATURE_AVX512_VBMI2	(16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
>> +#define X86_FEATURE_SHSTK		(16*32+ 7) /* Shadow Stack */
>>   #define X86_FEATURE_GFNI		(16*32+ 8) /* Galois Field New Instructions */
>>   #define X86_FEATURE_VAES		(16*32+ 9) /* Vector AES */
>>   #define X86_FEATURE_VPCLMULQDQ		(16*32+10) /* Carry-Less Multiplication Double Quadword */
>> @@ -370,6 +371,7 @@
>>   #define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */
>>   #define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */
>>   #define X86_FEATURE_ARCH_LBR		(18*32+19) /* Intel ARCH LBR */
>> +#define X86_FEATURE_IBT			(18*32+20) /* Indirect Branch Tracking */
>>   #define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */
>>   #define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */
>>   #define X86_FEATURE_FLUSH_L1D		(18*32+28) /* Flush L1D cache */
> 
> We don't sync the respective change in tools/ - Arnaldo doe
Got it.  I will remove this.

Yu-cheng
Borislav Petkov Nov. 6, 2020, 8:11 p.m. UTC | #3 
On Fri, Nov 06, 2020 at 11:48:26AM -0800, Yu, Yu-cheng wrote:
> I will drop it.  It has been re-based many times, and probably I
> accidentally introduced something else?

Yah, I think I added my tag to this version:

https://lkml.kernel.org/lkml/20181119214809.6086-3-yu-cheng.yu@intel.com/

Do you need to refresh on when tags get dropped?

See here: Documentation/process/submitting-patches.rst

You should verify the rest of the patchset too - tags are not
sticked to a patch forever.
Yu-cheng Yu Nov. 6, 2020, 8:14 p.m. UTC | #4 
On 11/6/2020 12:11 PM, Borislav Petkov wrote:
> On Fri, Nov 06, 2020 at 11:48:26AM -0800, Yu, Yu-cheng wrote:
>> I will drop it.  It has been re-based many times, and probably I
>> accidentally introduced something else?
> 
> Yah, I think I added my tag to this version:
> 
> https://lkml.kernel.org/lkml/20181119214809.6086-3-yu-cheng.yu@intel.com/
> 
> Do you need to refresh on when tags get dropped?
> 
> See here: Documentation/process/submitting-patches.rst
> 
> You should verify the rest of the patchset too - tags are not
> sticked to a patch forever.
> 

I will do that.

Yu-cheng
diff mbox series

Patch

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 2901d5df4366..c794e18e8a14 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -341,6 +341,7 @@ 
 #define X86_FEATURE_OSPKE		(16*32+ 4) /* OS Protection Keys Enable */
 #define X86_FEATURE_WAITPKG		(16*32+ 5) /* UMONITOR/UMWAIT/TPAUSE Instructions */
 #define X86_FEATURE_AVX512_VBMI2	(16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
+#define X86_FEATURE_SHSTK		(16*32+ 7) /* Shadow Stack */
 #define X86_FEATURE_GFNI		(16*32+ 8) /* Galois Field New Instructions */
 #define X86_FEATURE_VAES		(16*32+ 9) /* Vector AES */
 #define X86_FEATURE_VPCLMULQDQ		(16*32+10) /* Carry-Less Multiplication Double Quadword */
@@ -370,6 +371,7 @@ 
 #define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */
 #define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */
 #define X86_FEATURE_ARCH_LBR		(18*32+19) /* Intel ARCH LBR */
+#define X86_FEATURE_IBT			(18*32+20) /* Indirect Branch Tracking */
 #define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */
 #define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */
 #define X86_FEATURE_FLUSH_L1D		(18*32+28) /* Flush L1D cache */
diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c
index 3cbe24ca80ab..fec83cc74b9e 100644
--- a/arch/x86/kernel/cpu/cpuid-deps.c
+++ b/arch/x86/kernel/cpu/cpuid-deps.c
@@ -69,6 +69,8 @@  static const struct cpuid_dep cpuid_deps[] = {
 	{ X86_FEATURE_CQM_MBM_TOTAL,		X86_FEATURE_CQM_LLC   },
 	{ X86_FEATURE_CQM_MBM_LOCAL,		X86_FEATURE_CQM_LLC   },
 	{ X86_FEATURE_AVX512_BF16,		X86_FEATURE_AVX512VL  },
+	{ X86_FEATURE_SHSTK,			X86_FEATURE_XSAVES    },
+	{ X86_FEATURE_IBT,			X86_FEATURE_XSAVES    },
 	{}
 };
 
diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index 2901d5df4366..c794e18e8a14 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -341,6 +341,7 @@ 
 #define X86_FEATURE_OSPKE		(16*32+ 4) /* OS Protection Keys Enable */
 #define X86_FEATURE_WAITPKG		(16*32+ 5) /* UMONITOR/UMWAIT/TPAUSE Instructions */
 #define X86_FEATURE_AVX512_VBMI2	(16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
+#define X86_FEATURE_SHSTK		(16*32+ 7) /* Shadow Stack */
 #define X86_FEATURE_GFNI		(16*32+ 8) /* Galois Field New Instructions */
 #define X86_FEATURE_VAES		(16*32+ 9) /* Vector AES */
 #define X86_FEATURE_VPCLMULQDQ		(16*32+10) /* Carry-Less Multiplication Double Quadword */
@@ -370,6 +371,7 @@ 
 #define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */
 #define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */
 #define X86_FEATURE_ARCH_LBR		(18*32+19) /* Intel ARCH LBR */
+#define X86_FEATURE_IBT			(18*32+20) /* Indirect Branch Tracking */
 #define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */
 #define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */
 #define X86_FEATURE_FLUSH_L1D		(18*32+28) /* Flush L1D cache */