diff mbox series

[2/4] MIPS: fix tx39_flush_cache_page

Message ID 20211118093005.3121-2-huangpei@loongson.cn (mailing list archive)
State New
Headers show
Series [1/4] MIPS: rework local_t operation on MIPS64 | expand

Commit Message

Huang Pei Nov. 18, 2021, 9:30 a.m. UTC 
Indexed cache operation need KSEG0 address for safety and assume
that no dcache alias nor high memory

Signed-off-by: Huang Pei <huangpei@loongson.cn>
---
 arch/mips/mm/c-tx39.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index 03dfbb40ec73..49e4a16186ce 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -170,6 +170,7 @@  static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page
 	struct mm_struct *mm = vma->vm_mm;
 	pmd_t *pmdp;
 	pte_t *ptep;
+	unsigned long vaddr = phys_to_virt(pfn_to_phys(pfn));
 
 	/*
 	 * If ownes no valid ASID yet, cannot possibly have gotten
@@ -207,11 +208,14 @@  static void tx39_flush_cache_page(struct vm_area_struct *vma, unsigned long page
 	/*
 	 * Do indexed flush, too much work to get the (possible) TLB refills
 	 * to work correctly.
+	 *
+	 * Assuming that tx39 family do not support high memory, nor has
+	 * dcache alias, vaddr can index dcache directly and correctly
 	 */
 	if (cpu_has_dc_aliases || exec)
-		tx39_blast_dcache_page_indexed(page);
+		tx39_blast_dcache_page_indexed(vaddr);
 	if (exec)
-		tx39_blast_icache_page_indexed(page);
+		tx39_blast_icache_page_indexed(vaddr);
 }
 
 static void local_tx39_flush_data_cache_page(void * addr)