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David Alan Gilbert" , , , , , Brijesh Singh Subject: [PATCH v9 22/43] x86/sev: Move MSR-based VMGEXITs for CPUID to helper Date: Fri, 28 Jan 2022 11:17:43 -0600 Message-ID: <20220128171804.569796-23-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220128171804.569796-1-brijesh.singh@amd.com> References: <20220128171804.569796-1-brijesh.singh@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f0244a2f-c6ea-4382-6aca-08d9e28243b8 X-MS-TrafficTypeDiagnostic: BYAPR12MB2904:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4303; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: T6RDmDIlPIzGY4QWddHew2QCvmnTn5w50mEMNjJb8Bg1zwxiT6/BBdv8Yu88oQFpMWCw3gkDJubGBzsoGX29J9+RLh/GliVjjnnml2wlqvAK3aQ1ffVITphhkVTkqMgmNpixJU28DgpZF3MCv0SbZ+fxVbUMKOQoDuAWN6ME8rH3ebEpErEPjeClB2nvTWfT68Eosd1c0P4usDcg1lQIpT38UJY0bCYz4qzveDCWKmW2J8G1e9YJyuK0yUVrKuO3nnCpE5FHqa8gvjaIGjZM/tCCYwdlGB8vSIhPIlfC1gZfrsRnxBOpglweelxzeUH09gaDxGlOouAdyaG10eWW3Ih86rioBX8sjRXMzURW2HF1TNTWtj08PvR8B92KT1lS6IY5JPtjEK9o+yJOc0hvgLlSUrtFdcl+wcS6ascubK7n1Xk1yhVUwberVNr06d5XA+vb3MqUhIoymG7N6x1O2YaCd/hsXVZHaI3kxD0M6quUPhyNMTBJOd18PcpVq+ODxRUemDFXnRcwa/7M+5xRLH04YM7+rsWlP+sbxbdb0u2N1E0djGhtwJ8k3nqvoO0iR8nlCh6Q/dW421yG03tvGW6+bskntnDfbv/kOXVM7TgveKItdV8oZ+w4mRKlP1fCW7paWTn8yJGbipiHNRro8b/4sRNVlakvwJBtvlTFCCHjF4dcdHcHXgFIkZOcSB0LUCxLI9ImYyUX/zkyIHq43KMVurae19uo+83EwFcVVUM= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(36840700001)(46966006)(5660300002)(2616005)(47076005)(2906002)(7696005)(36756003)(4326008)(8676002)(86362001)(40460700003)(316002)(70586007)(8936002)(110136005)(54906003)(70206006)(426003)(336012)(356005)(82310400004)(26005)(44832011)(81166007)(36860700001)(7406005)(7416002)(16526019)(1076003)(186003)(83380400001)(6666004)(508600001)(36900700001)(2101003)(20210929001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jan 2022 17:18:55.8327 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f0244a2f-c6ea-4382-6aca-08d9e28243b8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB2904 X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: 4833340018 X-Rspam-User: nil Authentication-Results: imf01.hostedemail.com; dkim=pass header.d=amd.com header.s=selector1 header.b="wH0oMo/Y"; dmarc=pass (policy=quarantine) header.from=amd.com; spf=pass (imf01.hostedemail.com: domain of brijesh.singh@amd.com designates 40.107.92.40 as permitted sender) smtp.mailfrom=brijesh.singh@amd.com X-Stat-Signature: q75ohe13ri9p8ombxiaidgjcceqxa657 X-HE-Tag: 1643390340-180258 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Michael Roth This code will also be used later for SEV-SNP-validated CPUID code in some cases, so move it to a common helper. Signed-off-by: Michael Roth Signed-off-by: Brijesh Singh --- arch/x86/kernel/sev-shared.c | 62 +++++++++++++++++++++--------------- 1 file changed, 36 insertions(+), 26 deletions(-) diff --git a/arch/x86/kernel/sev-shared.c b/arch/x86/kernel/sev-shared.c index 3aaef1a18ffe..633f1f93b6e1 100644 --- a/arch/x86/kernel/sev-shared.c +++ b/arch/x86/kernel/sev-shared.c @@ -194,6 +194,36 @@ enum es_result sev_es_ghcb_hv_call(struct ghcb *ghcb, bool set_ghcb_msr, return verify_exception_info(ghcb, ctxt); } +static int __sev_cpuid_hv(u32 func, int reg_idx, u32 *reg) +{ + u64 val; + + if (!reg) + return 0; + + sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(func, reg_idx)); + VMGEXIT(); + val = sev_es_rd_ghcb_msr(); + if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) + return -EIO; + + *reg = (val >> 32); + + return 0; +} + +static int sev_cpuid_hv(u32 func, u32 *eax, u32 *ebx, u32 *ecx, u32 *edx) +{ + int ret; + + ret = __sev_cpuid_hv(func, GHCB_CPUID_REQ_EAX, eax); + ret = ret ? : __sev_cpuid_hv(func, GHCB_CPUID_REQ_EBX, ebx); + ret = ret ? : __sev_cpuid_hv(func, GHCB_CPUID_REQ_ECX, ecx); + ret = ret ? : __sev_cpuid_hv(func, GHCB_CPUID_REQ_EDX, edx); + + return ret; +} + /* * Boot VC Handler - This is the first VC handler during boot, there is no GHCB * page yet, so it only supports the MSR based communication with the @@ -202,39 +232,19 @@ enum es_result sev_es_ghcb_hv_call(struct ghcb *ghcb, bool set_ghcb_msr, void __init do_vc_no_ghcb(struct pt_regs *regs, unsigned long exit_code) { unsigned int fn = lower_bits(regs->ax, 32); - unsigned long val; + u32 eax, ebx, ecx, edx; /* Only CPUID is supported via MSR protocol */ if (exit_code != SVM_EXIT_CPUID) goto fail; - sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_EAX)); - VMGEXIT(); - val = sev_es_rd_ghcb_msr(); - if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) + if (sev_cpuid_hv(fn, &eax, &ebx, &ecx, &edx)) goto fail; - regs->ax = val >> 32; - sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_EBX)); - VMGEXIT(); - val = sev_es_rd_ghcb_msr(); - if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) - goto fail; - regs->bx = val >> 32; - - sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_ECX)); - VMGEXIT(); - val = sev_es_rd_ghcb_msr(); - if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) - goto fail; - regs->cx = val >> 32; - - sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_EDX)); - VMGEXIT(); - val = sev_es_rd_ghcb_msr(); - if (GHCB_RESP_CODE(val) != GHCB_MSR_CPUID_RESP) - goto fail; - regs->dx = val >> 32; + regs->ax = eax; + regs->bx = ebx; + regs->cx = ecx; + regs->dx = edx; /* * This is a VC handler and the #VC is only raised when SEV-ES is