| Message ID | 20220712231328.5294-2-kirill.shutemov@linux.intel.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Linear Address Masking enabling | expand |
On Wed, Jul 13, 2022 at 1:13 AM Kirill A. Shutemov <kirill.shutemov@linux.intel.com> wrote: > > The mask must not include bits above physical address mask. These bits > are reserved and can be used for other things. Bits 61 and 62 are used > for Linear Address Masking. > > Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> > Reviewed-by: Rick Edgecombe <rick.p.edgecombe@intel.com> Reviewed-by: Alexander Potapenko <glider@google.com> Tested-by: Alexander Potapenko <glider@google.com> > --- > arch/x86/include/asm/processor-flags.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/x86/include/asm/processor-flags.h b/arch/x86/include/asm/processor-flags.h > index 02c2cbda4a74..a7f3d9100adb 100644 > --- a/arch/x86/include/asm/processor-flags.h > +++ b/arch/x86/include/asm/processor-flags.h > @@ -35,7 +35,7 @@ > */ > #ifdef CONFIG_X86_64 > /* Mask off the address space ID and SME encryption bits. */ > -#define CR3_ADDR_MASK __sme_clr(0x7FFFFFFFFFFFF000ull) > +#define CR3_ADDR_MASK __sme_clr(PHYSICAL_PAGE_MASK) > #define CR3_PCID_MASK 0xFFFull > #define CR3_NOFLUSH BIT_ULL(63) > > -- > 2.35.1 >
> -----Original Message----- > From: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> > Sent: Wednesday, July 13, 2022 07:13 > To: Dave Hansen <dave.hansen@linux.intel.com>; Lutomirski, Andy > <luto@kernel.org>; Peter Zijlstra <peterz@infradead.org> > Cc: x86@kernel.org; Kostya Serebryany <kcc@google.com>; Andrey Ryabinin > <ryabinin.a.a@gmail.com>; Andrey Konovalov <andreyknvl@gmail.com>; > Alexander Potapenko <glider@google.com>; Taras Madan > <tarasmadan@google.com>; Dmitry Vyukov <dvyukov@google.com>; H . J . Lu > <hjl.tools@gmail.com>; Andi Kleen <ak@linux.intel.com>; Edgecombe, Rick P > <rick.p.edgecombe@intel.com>; linux-mm@kvack.org; linux- > kernel@vger.kernel.org; Kirill A. Shutemov <kirill.shutemov@linux.intel.com> > Subject: [PATCHv5 01/13] x86/mm: Fix CR3_ADDR_MASK > > The mask must not include bits above physical address mask. These bits are > reserved and can be used for other things. Bits 61 and 62 are used for Linear > Address Masking. > > Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> > Reviewed-by: Rick Edgecombe <rick.p.edgecombe@intel.com> > --- > arch/x86/include/asm/processor-flags.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/x86/include/asm/processor-flags.h > b/arch/x86/include/asm/processor-flags.h > index 02c2cbda4a74..a7f3d9100adb 100644 > --- a/arch/x86/include/asm/processor-flags.h > +++ b/arch/x86/include/asm/processor-flags.h > @@ -35,7 +35,7 @@ > */ [Hu, Robert] The comments above these #define's, explaining CR3 layout, can be updated on the new CR3 bits as well? > #ifdef CONFIG_X86_64 > /* Mask off the address space ID and SME encryption bits. */ > -#define CR3_ADDR_MASK __sme_clr(0x7FFFFFFFFFFFF000ull) > +#define CR3_ADDR_MASK __sme_clr(PHYSICAL_PAGE_MASK) > #define CR3_PCID_MASK 0xFFFull > #define CR3_NOFLUSH BIT_ULL(63) > > -- > 2.35.1
diff --git a/arch/x86/include/asm/processor-flags.h b/arch/x86/include/asm/processor-flags.h index 02c2cbda4a74..a7f3d9100adb 100644 --- a/arch/x86/include/asm/processor-flags.h +++ b/arch/x86/include/asm/processor-flags.h @@ -35,7 +35,7 @@ */ #ifdef CONFIG_X86_64 /* Mask off the address space ID and SME encryption bits. */ -#define CR3_ADDR_MASK __sme_clr(0x7FFFFFFFFFFFF000ull) +#define CR3_ADDR_MASK __sme_clr(PHYSICAL_PAGE_MASK) #define CR3_PCID_MASK 0xFFFull #define CR3_NOFLUSH BIT_ULL(63)