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bh=X4gTGIoZDPD05YxRdFQZH/uA/i6Ep+mlgv+7pNzKT5k=; b=Stc4k6nNmjxaPWz69W1KOrnUO2 aaMutptGkXNCVe3gZKsAonPL4JoW3W7A5oCHi0/rqfQoIe1pv0H3qEZ+XeaC0EaOh/qHj+1w7bpGp UpPx3ppcsRKWQQtwJ8cZ3M0yFSBXUDTDRPvj9R4oB7u3tTuRDqc5svb6VxJZtURnq/jaG+IebhQPO YAnfQkUnzeVHiEM0ewjgdj9SnYp2VN37ZU9kmKKS4mAaYTq+AjynPZ6PbLUwjXI1gQWs5PtTrkzcm x1HExJ9B5grwqCSJoP7LcpaY2XrYuOuNzPWG1XZXKo28GpahAObdAB/eO7OBPkBEUGx/f3sA0kCG/ JteVmCHA==; Received: from willy by casper.infradead.org with local (Exim 4.94.2 #2 (Red Hat Linux)) id 1pWhku-000IXK-Dj; Mon, 27 Feb 2023 17:57:44 +0000 From: "Matthew Wilcox (Oracle)" To: linux-mm@kvack.org, linux-arch@vger.kernel.org Cc: "Matthew Wilcox (Oracle)" , linux-kernel@vger.kernel.org, linux-ia64@vger.kernel.org Subject: [PATCH v2 10/30] ia64: Implement the new page table range API Date: Mon, 27 Feb 2023 17:57:21 +0000 Message-Id: <20230227175741.71216-11-willy@infradead.org> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230227175741.71216-1-willy@infradead.org> References: <20230227175741.71216-1-willy@infradead.org> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Server: rspam03 X-Stat-Signature: 3to7epp7wpdaffj17exiccm6g3ggfkwn X-Rspamd-Queue-Id: 06B5718001F X-HE-Tag: 1677520665-605431 X-HE-Meta: U2FsdGVkX190v/qbofDDUSqjNpbT6k3DU5Nk9LIUYez8PfEk5mW2DXBEzMGc5VsK68O/sEMHqFLHZMm7VMv/VDnxhDZFKN7mtdcOQFQH5uXMij0hnvy/rDrQV8xn9SUPNf6v+P8svJEtGqgvPeft60jFBEyLpewgxYYT9dK6f5jbDIs60iHrtnt5/O98+sqEcUG2c8uOxldzgkf2htaTlIIY2WeNSUktQ7yVi6eMJQBGHdwSHu7h7YfYnVNly9TsW15ymXkj/G5xjAcsl8kXjNvfGHAXpwK139ITBKIi3fvFR1Ngh0n9oE8ALsyJlfuK8B6vJyVcm6S3WAXPR8XpWYo0ipkX7HkhRl/z1yVGGLxR9LPZ3LUzoAezlhV4inVl1CAGKEq1sU2S73A7TJu2oqwNM48LCN3f6d7XE+wgK1iOgZfWFQBPYubCuol6zHDbpcIARoTsxjyGdEq368l4mPluV65rq4kmPgyDv7eLGVF0fcKGjTQpiUg24Y0/XHsWlnktvHlihmSRRJthGfZgY0pOzD2fCIEhJu9C/uPos7fG6qMIGVzxbbiOcWAtZ+2d23j1Vln4IgFg3ao0snuKN7xOdQZYJVGqCrCAI7v+DVav8tA7NierECQqaPKrdSSGCLPnVkkAfzgIzTXtXZHdvy1+GPrthZtECdOw9X2jOSIcXUQ36Sr6rMaKFK1UoC4YWr2l9QH/H2ttR9x48lYUmFiKriZFUpdeXOFwZk489rCnJsR9j7YkGaFPr6LWFUnxQfknLsqnJGvtFC/PyTENfeh0gIZOhRMbJ9SZoEmYtaDW7MOycoH94dtS+RgF8Qa8yxEga2oyu7YiDnWO/1LU+u22z7ox6AB4Joz5stHMBaDMp4hCldaIFavuGl/k21eiXONSULIDqy68Zl0eRRcpXXDelSWYmRIIi5HJPLu/8kyPtTeZm0krMOQM3oG2FpQZuJogB1jbjixLVbSke75 TZ1+PWmr 0vVPw+GW4zhOZfP+chPl1QaE4Cn/pN39vw1fdwmyEruku+Pg0yWrbFwMiP/G++kTXDu+rubIrVjz33/bctv52Ql6kX55yfvhSfNQIVOQPtU+XP6qT/QDEvz9v0Y3TLPOuBonUXCwFud/Imz7tPKuV3L8REL+k/RIVuVOZuRyFCvVCN/R3SlR8qh3W6RB3Y/pkakax8vy4ojjo5ta5K11tmqK/foBoRXin00i3eFvKc88ATzKfcmXKkObHouohR7Tbmz1q X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Add set_ptes(), update_mmu_cache_range() and flush_dcache_folio(). Change the PG_arch_1 (aka PG_dcache_clean) flag from being per-page to per-folio, which makes arch_dma_mark_clean() and mark_clean() a little more exciting. Signed-off-by: Matthew Wilcox (Oracle) Cc: linux-ia64@vger.kernel.org --- arch/ia64/hp/common/sba_iommu.c | 26 +++++++++++++++----------- arch/ia64/include/asm/cacheflush.h | 14 ++++++++++---- arch/ia64/include/asm/pgtable.h | 14 +++++++++++++- arch/ia64/mm/init.c | 29 +++++++++++++++++++---------- 4 files changed, 57 insertions(+), 26 deletions(-) diff --git a/arch/ia64/hp/common/sba_iommu.c b/arch/ia64/hp/common/sba_iommu.c index 8ad6946521d8..48d475f10003 100644 --- a/arch/ia64/hp/common/sba_iommu.c +++ b/arch/ia64/hp/common/sba_iommu.c @@ -798,22 +798,26 @@ sba_io_pdir_entry(u64 *pdir_ptr, unsigned long vba) #endif #ifdef ENABLE_MARK_CLEAN -/** +/* * Since DMA is i-cache coherent, any (complete) pages that were written via * DMA can be marked as "clean" so that lazy_mmu_prot_update() doesn't have to * flush them when they get mapped into an executable vm-area. */ -static void -mark_clean (void *addr, size_t size) +static void mark_clean(void *addr, size_t size) { - unsigned long pg_addr, end; - - pg_addr = PAGE_ALIGN((unsigned long) addr); - end = (unsigned long) addr + size; - while (pg_addr + PAGE_SIZE <= end) { - struct page *page = virt_to_page((void *)pg_addr); - set_bit(PG_arch_1, &page->flags); - pg_addr += PAGE_SIZE; + struct folio *folio = virt_to_folio(addr); + ssize_t left = size; + size_t offset = offset_in_folio(folio, addr); + + if (offset) { + left -= folio_size(folio) - offset; + folio = folio_next(folio); + } + + while (left >= folio_size(folio)) { + set_bit(PG_arch_1, &folio->flags); + left -= folio_size(folio); + folio = folio_next(folio); } } #endif diff --git a/arch/ia64/include/asm/cacheflush.h b/arch/ia64/include/asm/cacheflush.h index 708c0fa5d975..eac493fa9e0d 100644 --- a/arch/ia64/include/asm/cacheflush.h +++ b/arch/ia64/include/asm/cacheflush.h @@ -13,10 +13,16 @@ #include #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 -#define flush_dcache_page(page) \ -do { \ - clear_bit(PG_arch_1, &(page)->flags); \ -} while (0) +static inline void flush_dcache_folio(struct folio *folio) +{ + clear_bit(PG_arch_1, &folio->flags); +} +#define flush_dcache_folio flush_dcache_folio + +static inline void flush_dcache_page(struct page *page) +{ + flush_dcache_folio(page_folio(page)); +} extern void flush_icache_range(unsigned long start, unsigned long end); #define flush_icache_range flush_icache_range diff --git a/arch/ia64/include/asm/pgtable.h b/arch/ia64/include/asm/pgtable.h index 21c97e31a28a..0c2be4ea664b 100644 --- a/arch/ia64/include/asm/pgtable.h +++ b/arch/ia64/include/asm/pgtable.h @@ -303,7 +303,18 @@ static inline void set_pte(pte_t *ptep, pte_t pteval) *ptep = pteval; } -#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) +static inline void set_ptes(struct mm_struct *mm, unsigned long addr, + pte_t *ptep, pte_t pte, unsigned int nr) +{ + for (;;) { + set_pte(ptep, pte); + if (--nr == 0) + break; + ptep++; + pte_val(pte) += PAGE_SIZE; + } +} +#define set_pte_at(mm, addr, ptep, pte) set_ptes(mm, add, ptep, pte, 1) /* * Make page protection values cacheable, uncacheable, or write- @@ -396,6 +407,7 @@ pte_same (pte_t a, pte_t b) return pte_val(a) == pte_val(b); } +#define update_mmu_cache_range(vma, address, ptep, nr) do { } while (0) #define update_mmu_cache(vma, address, ptep) do { } while (0) extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; diff --git a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c index 7f5353e28516..12aef25944aa 100644 --- a/arch/ia64/mm/init.c +++ b/arch/ia64/mm/init.c @@ -50,30 +50,39 @@ void __ia64_sync_icache_dcache (pte_t pte) { unsigned long addr; - struct page *page; + struct folio *folio; - page = pte_page(pte); - addr = (unsigned long) page_address(page); + folio = page_folio(pte_page(pte)); + addr = (unsigned long)folio_address(folio); - if (test_bit(PG_arch_1, &page->flags)) + if (test_bit(PG_arch_1, &folio->flags)) return; /* i-cache is already coherent with d-cache */ - flush_icache_range(addr, addr + page_size(page)); - set_bit(PG_arch_1, &page->flags); /* mark page as clean */ + flush_icache_range(addr, addr + folio_size(folio)); + set_bit(PG_arch_1, &folio->flags); /* mark page as clean */ } /* - * Since DMA is i-cache coherent, any (complete) pages that were written via + * Since DMA is i-cache coherent, any (complete) folios that were written via * DMA can be marked as "clean" so that lazy_mmu_prot_update() doesn't have to * flush them when they get mapped into an executable vm-area. */ void arch_dma_mark_clean(phys_addr_t paddr, size_t size) { - unsigned long pfn = PHYS_PFN(paddr); + struct folio *folio = page_folio(phys_to_page(paddr)); + ssize_t left = size; + size_t offset = offset_in_folio(folio, paddr); - do { + if (offset) { + left -= folio_size(folio) - offset; + folio = folio_next(folio); + } + + while (left >= (ssize_t)folio_size(folio)) { set_bit(PG_arch_1, &pfn_to_page(pfn)->flags); - } while (++pfn <= PHYS_PFN(paddr + size - 1)); + left -= folio_size(folio); + folio = folio_next(folio); + } } inline void