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bh=bgDXt1j338PLwuReLhtbxzMM/LqJBLyZGUvNk00hFLE=; b=MZG8P9QCVk6X6QUeTHsxN4ljba XHTJvll6JiCHqkrFufD6FkOaPVdMfdChmuIsYG6gPN/C0EtF8ZsJOFYFEH1aeBcwuCVsvT6cc6zYC kERWqlZqxcgCWvBS70G4o63hwFCq5a5JLvfaDSP47cYHd1mFAk1fwtqJ/1In2d8HC2ySTJuVnuQNW lGzpIRExrBET51YPs0VKertzPTTKR+WXGDup5hZEHoBb9ayQxwVwro9LZ0dfPFqtLQK6Q85qK5e7b Aj8Top+afwoUhwQOh16Hnac/FNf0S0cYWNl7KZwibvSYNIWcbo2rngPWYZgxF35kJkqJ6zw0rggUf HdbXC1nQ==; Received: from willy by casper.infradead.org with local (Exim 4.94.2 #2 (Red Hat Linux)) id 1pX7fJ-0018pu-IG; Tue, 28 Feb 2023 21:37:41 +0000 From: "Matthew Wilcox (Oracle)" To: linux-mm@kvack.org, linux-arch@vger.kernel.org Cc: "Matthew Wilcox (Oracle)" , linux-kernel@vger.kernel.org, Alexandre Ghiti , Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org Subject: [PATCH v3 20/34] riscv: Implement the new page table range API Date: Tue, 28 Feb 2023 21:37:23 +0000 Message-Id: <20230228213738.272178-21-willy@infradead.org> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230228213738.272178-1-willy@infradead.org> References: <20230228213738.272178-1-willy@infradead.org> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: AF2E11C001D X-Stat-Signature: e49zryao1ajwy8hiys6fnxtpjcx5ggpm X-HE-Tag: 1677620263-469594 X-HE-Meta: U2FsdGVkX19a147lQFr6V9dU45f/85XU3Q81U2nzMKOqs5NUjohy+URC7UCmHAFPjkO5zNP+NY9fR4kNyiObfNi6+nl37QKj3uIzmDIFy/lO7IVWn8usBCF4teT1yJQ6hslzS5bf3/yiJN4N75rF26Z7TYD1K7O98gJEmi2+KYVJccZ2L9aDlF/fUg31DHQjrk+21NQiyfAurGlGtHHNIYYTbX5JSVktMyW0h31+zyMgEHwTdrZj4VBQ8DhezqJvHwQmh43BIttcvHQmzoXjeMZNOW9j58IjsELhT1P/MopupDDTajrTTW7WUISkB4bcbckFTZ3LsmC3AOMTUOpZULn6XK3Jr0MflsexKyWn+KYgQSUC90U4Kvz5fW976VZw0ycortwCADBz1g0fLVBHsXk6Esw4BaKG5YfC7Bon5YmoBdVk0KX76iXjZG3r3VLoOtagCkYguddUEcJunTWM9+dsxDjLMvRTKWlftqhfB5iQ91HhkbNBnG7Sy88cYuoQqwvwqln1y1pxSjXscFnWki9pwLGcRaSdomP7G2dQP6bsoAQuEg5M8HTnsEUZFTegcKejOLqIJoYeMRdikBD3Q8M1v+3ENtsx1GYf6pcLt1TBJnSd5Lkz3XxYMRgnpQHwO4qUPFuidxj9a9tKZZnZJYqmgLHo1X6TRzQL+EY2D42YH3cVK4a9v0AGP8G7uLsjhm1+E9QkccSdBsApnNwHbSdn+Z8RmRtOmRaTwV3Bu3FkpbZtBKW1H3C/JaolSGHBnvojXQcK6b5s37zEFxWfRy7TAXGTtaSmQttb2NO//+s2Evpq7YtpFzDEE8WNWVkBh8r/agoznU2O58goCYROJHW9KntS6G/LydbJngTSJF4ifSBt20dCppA2kEv1+FHIH8XT6ki9e3/a2IViL2WkbT5bg8JPohCKnd/VQDVASo6zGacRacCMQxRz4FRiohprC1zffiDXBcP0YgMCJWL vFRux2ST kUcyB4Qh9aTu3htMFIL60Dg5juFMMuiizMaR1vQ6Rzx/EOlaGtbwjlQKC38v3lBUJO2gtWhKvMSgLYY2s3c0p9n4ZsGBuN67xZJoYsK0sOw2a4F2DLMH480rfqFFQPnEllEkDTr07iSHb6/y34KsTz7Yv16xriUZkKlIA8TI5vCxRpn2gj9JvMRlWenO0devIdJ/L76Ia2qXJrgchUlsziOS8ZgDx61bRmhLstthFwDHQLFuuvuwadGKryXiv7c1b6+ugOnS7oEp8ol/rrE3uQtMBGnZ1IoGIw5KbiVx2RA2JIr2wapq8WFNAiCImrKfRvkUTKKsADRTdx0XKyBoY90H+5D1NHMktXBMd8i0eWW3DXgV/LuPSA9bJiQ== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Add set_ptes(), update_mmu_cache_range() and flush_dcache_folio(). Change the PG_dcache_clean flag from being per-page to per-folio. Signed-off-by: Matthew Wilcox (Oracle) Reviewed-by: Alexandre Ghiti Cc: Paul Walmsley Cc: Palmer Dabbelt Cc: Albert Ou Cc: linux-riscv@lists.infradead.org Acked-by: Palmer Dabbelt --- arch/riscv/include/asm/cacheflush.h | 19 +++++++++---------- arch/riscv/include/asm/pgtable.h | 26 +++++++++++++++++++------- arch/riscv/mm/cacheflush.c | 11 ++--------- 3 files changed, 30 insertions(+), 26 deletions(-) diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index 03e3b95ae6da..10e5e96f09b5 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -15,20 +15,19 @@ static inline void local_flush_icache_all(void) #define PG_dcache_clean PG_arch_1 -static inline void flush_dcache_page(struct page *page) +static inline void flush_dcache_folio(struct folio *folio) { - /* - * HugeTLB pages are always fully mapped and only head page will be - * set PG_dcache_clean (see comments in flush_icache_pte()). - */ - if (PageHuge(page)) - page = compound_head(page); - - if (test_bit(PG_dcache_clean, &page->flags)) - clear_bit(PG_dcache_clean, &page->flags); + if (test_bit(PG_dcache_clean, &folio->flags)) + clear_bit(PG_dcache_clean, &folio->flags); } +#define flush_dcache_folio flush_dcache_folio #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 +static inline void flush_dcache_page(struct page *page) +{ + flush_dcache_folio(page_folio(page)); +} + /* * RISC-V doesn't have an instruction to flush parts of the instruction cache, * so instead we just flush the whole thing. diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h index b516f3b59616..3a3a776fc047 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -405,8 +405,8 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) /* Commit new configuration to MMU hardware */ -static inline void update_mmu_cache(struct vm_area_struct *vma, - unsigned long address, pte_t *ptep) +static inline void update_mmu_cache_range(struct vm_area_struct *vma, + unsigned long address, pte_t *ptep, unsigned int nr) { /* * The kernel assumes that TLBs don't cache invalid entries, but @@ -415,8 +415,11 @@ static inline void update_mmu_cache(struct vm_area_struct *vma, * Relying on flush_tlb_fix_spurious_fault would suffice, but * the extra traps reduce performance. So, eagerly SFENCE.VMA. */ - local_flush_tlb_page(address); + while (nr--) + local_flush_tlb_page(address + nr * PAGE_SIZE); } +#define update_mmu_cache(vma, addr, ptep) \ + update_mmu_cache_range(vma, addr, ptep, 1) #define __HAVE_ARCH_UPDATE_MMU_TLB #define update_mmu_tlb update_mmu_cache @@ -456,12 +459,21 @@ static inline void __set_pte_at(struct mm_struct *mm, set_pte(ptep, pteval); } -static inline void set_pte_at(struct mm_struct *mm, - unsigned long addr, pte_t *ptep, pte_t pteval) +static inline void set_ptes(struct mm_struct *mm, unsigned long addr, + pte_t *ptep, pte_t pteval, unsigned int nr) { - page_table_check_ptes_set(mm, addr, ptep, pteval, 1); - __set_pte_at(mm, addr, ptep, pteval); + page_table_check_ptes_set(mm, addr, ptep, pteval, nr); + + for (;;) { + __set_pte_at(mm, addr, ptep, pteval); + if (--nr == 0) + break; + ptep++; + addr += PAGE_SIZE; + pte_val(pteval) += 1 << _PAGE_PFN_SHIFT; + } } +#define set_pte_at(mm, addr, ptep, pte) set_ptes(mm, addr, ptep, pte, 1) static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index fcd6145fbead..e36a851e5788 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -81,16 +81,9 @@ void flush_icache_mm(struct mm_struct *mm, bool local) #ifdef CONFIG_MMU void flush_icache_pte(pte_t pte) { - struct page *page = pte_page(pte); + struct folio *folio = page_folio(pte_page(pte)); - /* - * HugeTLB pages are always fully mapped, so only setting head page's - * PG_dcache_clean flag is enough. - */ - if (PageHuge(page)) - page = compound_head(page); - - if (!test_bit(PG_dcache_clean, &page->flags)) { + if (!test_bit(PG_dcache_clean, &folio->flags)) { flush_icache_all(); set_bit(PG_dcache_clean, &page->flags); }