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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT097.mail.protection.outlook.com (10.13.172.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6477.29 via Frontend Transport; Mon, 12 Jun 2023 04:46:53 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Sun, 11 Jun 2023 23:45:51 -0500 From: Michael Roth To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Brijesh Singh Subject: [PATCH RFC v9 39/51] KVM: x86: Define RMP page fault error bits for #NPF Date: Sun, 11 Jun 2023 23:25:47 -0500 Message-ID: <20230612042559.375660-40-michael.roth@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230612042559.375660-1-michael.roth@amd.com> References: <20230612042559.375660-1-michael.roth@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT097:EE_|CH3PR12MB8259:EE_ X-MS-Office365-Filtering-Correlation-Id: e177e363-8050-4100-9f42-08db6b000b01 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jun 2023 04:46:53.1103 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e177e363-8050-4100-9f42-08db6b000b01 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT097.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8259 X-Rspam-User: X-Stat-Signature: ccqcgqxc6cuwyj1n6qajobbywpr9abyr X-Rspamd-Server: rspam07 X-Rspamd-Queue-Id: 37EB710000D X-HE-Tag: 1686545216-609421 X-HE-Meta: U2FsdGVkX1+M+Dga5wKrSFTXgRLOXPTO90XTY7Gxzn8AKJuI5qHlx3inIy9v5T6XBPPipB1PtfNsGK7OAHkKhOimhxfMs39U1tzpsIRfp6eAcQffL1E8mf05XFDB1rZ8U0vCpwkyWUAYmaS/atDIBa5SM2ZRXMcGbd9OTGGTCr1Qkt48VXSPI1tE0/5oI+v83zNLEHhokBfxsTLTRo9Tp2jxAkGf9vn6xmCOgl8IQ5zxtYfVVY07bVGjYjxAZhY7tGkMmKxfbUP6yjP7ix0fn1FUE8OuKnjPw/GO9xtAkzB9ABp/p2J4X2VYY9Jmj9dL2D41JvAKojPo3MzqXHpds5U0XT/Yok2oe8RL2gCT6B10RG4Zjn+albzo+Z6n2dS1G8MckoUc2csiLkvV34qWK8ejrP4WcjUIV+1C/oJ+9XSf1CSnHtd0kor3flwMnjNW8NiX6sft7uZuSIQWE3gFQD3gCr9axDAvE8giiGPEQszXY/172tYJPcQlhKwd+3miJxufZpkRgd6nwLGQYOSwZArD3diaby5L6G9B1CpEuS/vLC/FoKbSvC6WpMGgnknjqzmm25ANinvTTX2kZSr4hB64bE39OL4Mhm69U7K9Jdbfchzv+jpCfsbv7eaDCZQCFF6A0ZWCUvZ7KkkkW7SMR1zpFta1pRw2/EUEGEEDGEjEZLzrhhGMwgESxaKHDlFIV/4p8FNKv+Tdgx5s9CdM0MREjNfv+mTQ1bUDECOMwdXgKWjC8mRHCzfWlb01rVIMNsPRsqFqyno1cLJ/qtitz91y7UMVWjm0NWN3RiHCyQtj7OdKCIIZ02qnqixjmZyz945QSONjSHdB9qTia9mI87zkdDfrVFmVXyt6vlhH/5PawkMF+Gmi2IQS+AWKI1B/f0O4+UTrh29eD7pOquywddXSg5qRjZzpQTS4jAtTPYj88xgkkA1jfb5CW4+FJLq8TmKlzRMzjrGLpfEqeXP LnIKKP9v EgSvKIEqUhE6QERzffNGoiWiMCFfZjbTwyg7fSF6co5jbTdBEAi76H08/fKGLm29YGej73AkSmP9l4znGT9Xtq+jRla7T8VjEHP4waQmhzl3e6u0kQ1fKYuT+basYOPq16D7AQ985w6+dAWRTArB8WXoXFRDZYb5Prpzr+QRwqE/DTLxFi7ij4BMesdzTxzws40ihfoQmhwNDFl2kIhn5TDVKWUVIAQegL8hZphqBOWdBlSBccIkxRwWlxs8Un3U0qwxOthOZUOqGiJDVIAgS7igvb8tPsH3EEYcOYpRBoH36CHMvR12FF/+C3k9WGckK2e09DLvWi6ZRKnzPUKjRiweg3Q== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Brijesh Singh When SEV-SNP is enabled globally, the hardware places restrictions on all memory accesses based on the RMP entry, whether the hypervisor or a VM, performs the accesses. When hardware encounters an RMP access violation during a guest access, it will cause a #VMEXIT(NPF). See APM2 section 16.36.10 for more details. Signed-off-by: Brijesh Singh Signed-off-by: Ashish Kalra Signed-off-by: Michael Roth --- arch/x86/include/asm/kvm_host.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 026bfc4446ee..2fcd309fd9fb 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -253,9 +253,13 @@ enum x86_intercept_stage; #define PFERR_FETCH_BIT 4 #define PFERR_PK_BIT 5 #define PFERR_SGX_BIT 15 +#define PFERR_GUEST_RMP_BIT 31 #define PFERR_GUEST_FINAL_BIT 32 #define PFERR_GUEST_PAGE_BIT 33 #define PFERR_IMPLICIT_ACCESS_BIT 48 +#define PFERR_GUEST_ENC_BIT 34 +#define PFERR_GUEST_SIZEM_BIT 35 +#define PFERR_GUEST_VMPL_BIT 36 #define PFERR_PRESENT_MASK BIT(PFERR_PRESENT_BIT) #define PFERR_WRITE_MASK BIT(PFERR_WRITE_BIT) @@ -267,6 +271,10 @@ enum x86_intercept_stage; #define PFERR_GUEST_FINAL_MASK BIT_ULL(PFERR_GUEST_FINAL_BIT) #define PFERR_GUEST_PAGE_MASK BIT_ULL(PFERR_GUEST_PAGE_BIT) #define PFERR_IMPLICIT_ACCESS BIT_ULL(PFERR_IMPLICIT_ACCESS_BIT) +#define PFERR_GUEST_RMP_MASK BIT_ULL(PFERR_GUEST_RMP_BIT) +#define PFERR_GUEST_ENC_MASK BIT_ULL(PFERR_GUEST_ENC_BIT) +#define PFERR_GUEST_SIZEM_MASK BIT_ULL(PFERR_GUEST_SIZEM_BIT) +#define PFERR_GUEST_VMPL_MASK BIT_ULL(PFERR_GUEST_VMPL_BIT) #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \ PFERR_WRITE_MASK | \