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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jun 2023 04:58:53.4756 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fc23a14d-6efd-4d36-2bca-08db6b01b86a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT078.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7829 X-Rspamd-Server: rspam09 X-Rspamd-Queue-Id: 1EE162000B X-Stat-Signature: ufecms8uczdnjhea4odxiifna4r6bg1m X-Rspam-User: X-HE-Tag: 1686545935-752762 X-HE-Meta: U2FsdGVkX19Sy8PFxGVUO8L99YKyf66YBsdInmoL0vzXXP3VbMVD9KRPCd/0w34JKmv8LYQ88MIn1vHd7rZ+ffyZE3CfSAzsI1UTYso1gD7kW/25Lc6xo5klviUiOggFHyAJfodE026NEUcciBv8WvvqFmzWrTjm55nJMVAUtmpgQz6EtWB5ixmGJTPPjFBTi3Cl4UeR6CvrzvfN5bxrKYTimKITzNX1BrXPa/f4qefvCgOnRlyqd5WowX1PL7X6+M7S1jXaXEYv8llelvee7NtR4CjOhVeQhUsM2ywOajKhl/9CbrDHJ+h5KY+Q6wHtyDGhIM4HLHjRG/HTnzgI4Ukp8DpsO8DX0bPka1FjhlM699fqYrJTjA7K6MBsmeQEW4FxNbbRLytLag5l1lS8cqIshQqvfnyE8tlYozNlukKHpRuBgjurckefPbJe9cbuz6av/ptKCLanI17ZLUE/6CD6FZEGMV6T0wTD/UHXwjKdT0H2RuqhD7XMOavnt0J6iWKzzsa/ON7Er6ve/PsFtB1vvJgQEKXL5T92LF3Yzw8cP++vwBYIp9XqId/ZQNE88cv6ZTCU4CrrXLDUtJmDU4Csp80wTxMRCB3LngcL9lr7X+Hr8dEMUwwVe1qdmoFf80aB8mI9B21UEMqKxwAYhP4BD8eCoddSYTCHmE7iHsWpJ7+mP8My7NGw3EsL/VWDhsXq8mc/KkeSbyPsySNCdZsXjIh9CDGbDAcOrL7FJkSUah4ei+SUP7fgoEII/4bl7ktlcuQEV9ZlOG6hNuZEjKUs6nsWr5IS9VeGZiEo6MJY4UvpztQZSdn6Xr8fuyICJ+T6R2WXWZ58B4FHjqEHz3cTL2/L/bKb5NmmQegITkOpXkBIDsL2lWHgFZXJkCsZDsTtSQCZ4eYnit++0fUL1aUVmp/9hSjMP3kcVK92KXeY2ahEpHjVmDMA80JM6Sgn09pKimQD5LstNolbhsP U7Yv51ss 8BVTLSGB5zPXV3RT1L+EL9F8pd7/WnIJ+DI9T5PC9mXVIIqhhJYDsKkMtrZMjB7OzQhX5/jeVSlzkPlgb57C8NpuLiRQNWc26V7DcAoOB3lJmdsfcjFgpaT9r5XP0Znye/jR92s8VR6REAPloQf+Y4mhVykG207iSiNgmHZAXSkPhCaBKv3//W8E2rpo5pO33h3JAxyJhUO2UfF7G9TqNyARY/YyDxWRXzkS7f8sZLGCX9cMxNc6BseEBUiAifmtivDIywc/MPrPuSRMKQzHD0mS9YU/pQBxjcKmgy3GNkfKG7bsWsiofiakdUzY3NiLblySNZRbpYgDbwVAd/JmZRhuufjbXTq68+g0N8uG83zGGLGU+acZdLWdOxQ== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: From: Brijesh Singh Add CPU feature detection for Secure Encrypted Virtualization with Secure Nested Paging. This feature adds a strong memory integrity protection to help prevent malicious hypervisor-based attacks like data replay, memory re-mapping, and more. Signed-off-by: Brijesh Singh Signed-off-by: Jarkko Sakkinen Signed-off-by: Ashish Kalra Signed-off-by: Michael Roth --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/amd.c | 5 +++-- tools/arch/x86/include/asm/cpufeatures.h | 1 + 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 97327a1e3aff..b60b32f47884 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -431,6 +431,7 @@ #define X86_FEATURE_SEV (19*32+ 1) /* AMD Secure Encrypted Virtualization */ #define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* "" VM Page Flush MSR is supported */ #define X86_FEATURE_SEV_ES (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */ +#define X86_FEATURE_SEV_SNP (19*32+ 4) /* AMD Secure Encrypted Virtualization - Secure Nested Paging */ #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* "" Virtual TSC_AUX */ #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */ diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 95cdd08c4cbb..a79774181f22 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -558,8 +558,8 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) * SME feature (set in scattered.c). * If the kernel has not enabled SME via any means then * don't advertise the SME feature. - * For SEV: If BIOS has not enabled SEV then don't advertise the - * SEV and SEV_ES feature (set in scattered.c). + * For SEV: If BIOS has not enabled SEV then don't advertise SEV and + * any additional functionality based on it. * * In all cases, since support for SME and SEV requires long mode, * don't advertise the feature under CONFIG_X86_32. @@ -594,6 +594,7 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) clear_sev: setup_clear_cpu_cap(X86_FEATURE_SEV); setup_clear_cpu_cap(X86_FEATURE_SEV_ES); + setup_clear_cpu_cap(X86_FEATURE_SEV_SNP); } } diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index b89005819cd5..b4f11a500470 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -424,6 +424,7 @@ #define X86_FEATURE_SEV (19*32+ 1) /* AMD Secure Encrypted Virtualization */ #define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* "" VM Page Flush MSR is supported */ #define X86_FEATURE_SEV_ES (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */ +#define X86_FEATURE_SEV_SNP (19*32+ 4) /* AMD Secure Encrypted Virtualization - Secure Nested Paging */ #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* "" Virtual TSC_AUX */ #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */