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bh=Ppdmkbhn3pdci2A5T+8/PDoAOO4tRHFDpMfgtHEjIi8=; b=lPuyuN9/kfzzegkfuFmcsaU9fF Lc/9z5kp4JaqUHiiCtO4bct9lDeuZEuBbGVmD75jHyod+q5OS9/E33T+yVfXQq56C7GARJp6DyjIR o3UuxEY0HJslmfgdR+bF9veKcWu1b4C+HRsH7/UYSDnz5jP8cDnvYdYrQQcgREzKagDeWJNfCOHL1 ZwfyY7vuDOw4waS2NW2CPa2NjUUcSm0wjYA9qAvsyhqfVtNiBplyeqAYGg44dbIwl3lVtJ3jc3T7f oQ1o/qpbmedQ7/dlvUjfDX9dJeYTDR6bleepVfHIh67aOcZYvrfvBEeXRe2a+li5dwtQXgjm2SZ/3 VDeFgVJQ==; Received: from willy by casper.infradead.org with local (Exim 4.94.2 #2 (Red Hat Linux)) id 1qIxjS-00Euon-AG; Mon, 10 Jul 2023 20:43:42 +0000 From: "Matthew Wilcox (Oracle)" To: Andrew Morton Cc: "Matthew Wilcox (Oracle)" , linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, Catalin Marinas , Mike Rapoport , linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 10/38] arm64: Implement the new page table range API Date: Mon, 10 Jul 2023 21:43:11 +0100 Message-Id: <20230710204339.3554919-11-willy@infradead.org> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230710204339.3554919-1-willy@infradead.org> References: <20230710204339.3554919-1-willy@infradead.org> MIME-Version: 1.0 X-Rspamd-Server: rspam09 X-Rspamd-Queue-Id: 3000C4000E X-Stat-Signature: wnz8qfpb5nbnyhcft8pf3sxk3sxec1na X-Rspam-User: X-HE-Tag: 1689021824-98836 X-HE-Meta: U2FsdGVkX19H6NcrEBM1zNLZNpguvW+5ZJkDL6vd8x/JBxmbeMg1KQu3UuRl1G9ndJFSIo/ebY6gbMQ3pityaO+zx7U5bfF27/eRPvSXXqeWZtubydpN2CD5PUgzjHuiab6Px32X2ey384yzrMYUBksuUlKS/O9IUkm+X4Glq8g3i5gkY6TqzhU0u7f9UkE84BJLzZtSNrm+exPm9LwCwVhTlRsmE0cobsx+L45KhqBzH2YY52BV9V6kS1DYoV/+DIyiSv11/UYnMoInoP6fMl9y1eFpZdSDQHF6dObgxejH0exiIrF7GG3XOA0tXTK8kEeVfC9D7pxIqV4HYcPkq3lDo2ubSRwBo9I1o1aBChNuELyLdxtqZBBrmDqA431plvW/AXbaTXJK12L7oKEb3SCkHPbdRz/yr3IUy/3PdYZcCoj0TuwmmkNF2ALUexcQHSqMfdLDZ+Z/0ATpniHLjfEjtp44HlWILTizyLy49ygZ8TIgfj11ZCaXCqJDorb7752g5EEHnsrQOXsv2XKbdD9v+H4L6Bvsaf267HLYozKL3Ozpb5aTJaOULBLcBmB3ry4PdTz4jvLoE5b7ULrdwE0uy3rS37LhVCrYI08ARnSepzbZ2/rCmSFrPZhXIFr9s0sPFzP6a+LNuRLsNgWPx2/gd65MRCxhbHz1Wl3i9446Xa+OOtP7GAdPKzTUyevESwI06rx216xO64eLU83CdTQflBt9sQVBueJ+qFL0709nzJxUMp+kBjTNjwL+zif2coVkrFUh3hpdTRm8Z1N9PRwqE8QPndkN0q6X5JxtgMksEZMA+tZ8mXE136vtBDrZi09cH1UrVkIaT2q+ehETjOXCr1U9eraQz/f75G9cdHi+LHulhSI9qG3J32CVoGdApN2cj0/8eJT1eKE6tbuYct32ueGFnlyVyQz8TBpAPD/doCafFm7cQgskrrhTbGGQklRt+kvHTmfsQQHQznw Bld4xy3t AgGHNdEGSNjjwLqQyCKtkTB9GZhfgyypRc3C87bTk1j4dfXRHDmgF57rO/SfNwARdt8yvrpxP5FT3OnmzhVK4AlSESE+Gfk8h/9pzEYGb0MfNRkcK+PrD2WgDKx4xl9KlzmPqZ1Rm7vCdymWM7N81qqYmVYF1WZR1OX40u0bFpSbtyuXHDWVZDKihFyQJU+g2n1g72EV2WKB92e7su0+esZ/cNzQJV3abM4vMPqmq+T4Q4ST40Ij9XxmnCNMQ/y7hy4pKr0HNHhjz+9hKVc2w6jIaSSWlkXFk2rYri4uqGTkM62E= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Add set_ptes(), update_mmu_cache_range() and flush_dcache_folio(). Change the PG_dcache_clean flag from being per-page to per-folio. Signed-off-by: Matthew Wilcox (Oracle) Reviewed-by: Catalin Marinas Acked-by: Mike Rapoport (IBM) Cc: linux-arm-kernel@lists.infradead.org --- arch/arm64/include/asm/cacheflush.h | 4 +++- arch/arm64/include/asm/pgtable.h | 26 +++++++++++++++------ arch/arm64/mm/flush.c | 36 +++++++++++------------------ 3 files changed, 36 insertions(+), 30 deletions(-) diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h index 37185e978aeb..d115451ed263 100644 --- a/arch/arm64/include/asm/cacheflush.h +++ b/arch/arm64/include/asm/cacheflush.h @@ -114,7 +114,7 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *, #define copy_to_user_page copy_to_user_page /* - * flush_dcache_page is used when the kernel has written to the page + * flush_dcache_folio is used when the kernel has written to the page * cache page at virtual address page->virtual. * * If this page isn't mapped (ie, page_mapping == NULL), or it might @@ -127,6 +127,8 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *, */ #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 extern void flush_dcache_page(struct page *); +void flush_dcache_folio(struct folio *); +#define flush_dcache_folio flush_dcache_folio static __always_inline void icache_inval_all_pou(void) { diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index a44a150e0318..c1c4abf75217 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -345,12 +345,21 @@ static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, set_pte(ptep, pte); } -static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, - pte_t *ptep, pte_t pte) -{ - page_table_check_ptes_set(mm, addr, ptep, pte, 1); - return __set_pte_at(mm, addr, ptep, pte); +static inline void set_ptes(struct mm_struct *mm, unsigned long addr, + pte_t *ptep, pte_t pte, unsigned int nr) +{ + page_table_check_ptes_set(mm, addr, ptep, pte, nr); + + for (;;) { + __set_pte_at(mm, addr, ptep, pte); + if (--nr == 0) + break; + ptep++; + addr += PAGE_SIZE; + pte_val(pte) += PAGE_SIZE; + } } +#define set_ptes set_ptes /* * Huge pte definitions. @@ -1049,8 +1058,9 @@ static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio) /* * On AArch64, the cache coherency is handled via the set_pte_at() function. */ -static inline void update_mmu_cache(struct vm_area_struct *vma, - unsigned long addr, pte_t *ptep) +static inline void update_mmu_cache_range(struct vm_fault *vmf, + struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, + unsigned int nr) { /* * We don't do anything here, so there's a very small chance of @@ -1059,6 +1069,8 @@ static inline void update_mmu_cache(struct vm_area_struct *vma, */ } +#define update_mmu_cache(vma, addr, ptep) \ + update_mmu_cache_range(NULL, vma, addr, ptep, 1) #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) #ifdef CONFIG_ARM64_PA_BITS_52 diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c index 4e6476094952..013eead9b695 100644 --- a/arch/arm64/mm/flush.c +++ b/arch/arm64/mm/flush.c @@ -51,20 +51,13 @@ void copy_to_user_page(struct vm_area_struct *vma, struct page *page, void __sync_icache_dcache(pte_t pte) { - struct page *page = pte_page(pte); + struct folio *folio = page_folio(pte_page(pte)); - /* - * HugeTLB pages are always fully mapped, so only setting head page's - * PG_dcache_clean flag is enough. - */ - if (PageHuge(page)) - page = compound_head(page); - - if (!test_bit(PG_dcache_clean, &page->flags)) { - sync_icache_aliases((unsigned long)page_address(page), - (unsigned long)page_address(page) + - page_size(page)); - set_bit(PG_dcache_clean, &page->flags); + if (!test_bit(PG_dcache_clean, &folio->flags)) { + sync_icache_aliases((unsigned long)folio_address(folio), + (unsigned long)folio_address(folio) + + folio_size(folio)); + set_bit(PG_dcache_clean, &folio->flags); } } EXPORT_SYMBOL_GPL(__sync_icache_dcache); @@ -74,17 +67,16 @@ EXPORT_SYMBOL_GPL(__sync_icache_dcache); * it as dirty for later flushing when mapped in user space (if executable, * see __sync_icache_dcache). */ -void flush_dcache_page(struct page *page) +void flush_dcache_folio(struct folio *folio) { - /* - * HugeTLB pages are always fully mapped and only head page will be - * set PG_dcache_clean (see comments in __sync_icache_dcache()). - */ - if (PageHuge(page)) - page = compound_head(page); + if (test_bit(PG_dcache_clean, &folio->flags)) + clear_bit(PG_dcache_clean, &folio->flags); +} +EXPORT_SYMBOL(flush_dcache_folio); - if (test_bit(PG_dcache_clean, &page->flags)) - clear_bit(PG_dcache_clean, &page->flags); +void flush_dcache_page(struct page *page) +{ + flush_dcache_folio(page_folio(page)); } EXPORT_SYMBOL(flush_dcache_page);