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bh=mgSRsBuZwAxpA55hxS9bw6q/jUx3mEY9QYeL/14gdEs=; b=m2nhsFKC/z/frhghKqW4xYfvlf 1e219T68traQOXiSiDDZ4G8arXqZoZyLAbAFiBETBn60Ivi1fORm0n/IbuWcSIPfscbWxp3GLBFLK EQRrHCWD6OT/5mToOLh7gsyWzsccpl56Ga9sI028K2qtHA8dnLiucAZpyKjpzXDGD7kKcSrOQxggu YD95HWIrKmmJLT21MmN7jwxuYRna42EpEB+ubdoyTT3/9W1VXGHh5yVs991G1XbJdmEX3Myi6QnBn 1XAvszyFtItLZgM9oplYfy0/nLBk4V53r8vLSVbmyj281T9AMRqEZrRJ8Amf5t6w9ZFxKh4m+MP89 OOwZk8Yw==; Received: from willy by casper.infradead.org with local (Exim 4.94.2 #2 (Red Hat Linux)) id 1qRDY8-00Ffj4-TB; Wed, 02 Aug 2023 15:14:08 +0000 From: "Matthew Wilcox (Oracle)" To: Andrew Morton Cc: "Matthew Wilcox (Oracle)" , linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, Catalin Marinas , Mike Rapoport , linux-arm-kernel@lists.infradead.org Subject: [PATCH v6 10/38] arm64: Implement the new page table range API Date: Wed, 2 Aug 2023 16:13:38 +0100 Message-Id: <20230802151406.3735276-11-willy@infradead.org> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230802151406.3735276-1-willy@infradead.org> References: <20230802151406.3735276-1-willy@infradead.org> MIME-Version: 1.0 X-Rspamd-Queue-Id: 6C9B91C000D X-Rspam-User: X-Stat-Signature: c1hudd9pcxka4nxf9ngnpft6askwxtj4 X-Rspamd-Server: rspam03 X-HE-Tag: 1690989266-494057 X-HE-Meta: U2FsdGVkX18zo3S/F99nrAfUP03jDK5ZEXgLkNW/XCdXvWZSuw9L/RWTyhp6Oa829psBdthhkDB6cw0IDzMTEX8CZ6wA9xQmml4Q/eMTuqEfw+1kZ+3bj+yoOtqhbOVcUTC0R0ThFfDWehSUpr1zo6mYVtgltmrcmJDTPOF3ss+SwbmS7rwLlpRWHSgQXeL2CVRL85fYBh5Ba1BQj6bJfjkaxPrrnmwgTUmfGRdvyReSa1p/27kYWXfzuDBMjwq5kwEgvtkWQ4PlUXcWo/CPpv7QE+rttTC4+wWliPc3CZWVUZ+F1VVGb6e3Lej1YrZ16kmNWzM81aJ35O/aTCYh+tMTyus19MJpr8S6aZlvCFRhahqo3J88Pkzw8htdAhDclYc3pllg4kgeBp/XYfrl4Zm1A1FvAesjhcqz3X5GlvsxY4BZNSu4DFnlUABfYflTTrKrc631DIggmVJQThfEEQd0jmFcMOLi3B5lb17okO4ZFDe0GYqH82j1vnjHS6z3N3qkEWfCJo2Lfs6cQq+tK9uJDO0S6iADgl1h3HLxv++Tt/YhlMO/lBAXKiswGkZ4ake5KSaWkRBF2dtupD/VJEgAJMOA8zPJjqBGXxh4ZBL5OsL6PT+qy6bqKh09S8CLUxZF0J8GJdTsBIfeWN3fV8eVdEqk1IaChUHj0FNVX8TQq6WcjXlxvIxxba2W0Yw6xrjU+L10HEnwKyLHLwiojbJuwBSH98VZkxkiFS+7E13Am0o53m2ALIljE6eM7XqNnwj1LIeucxeHCL01qedRZ5Fyyrp+aa89D3O3hirJQCqfB8sOvwr/eqmB1nVzlWvDHmRv+8BjB37wdjlxuAissjT1ZGfUOr6A7QML3OovnUHAufI2hxhCQI09uCtAO6GsQJ5dRz8Jt2Eq9DupsexlkSyaMPah0HNsYs/7EEM4SBBpVPd7kTOlpL2HjASpI5H1esDejN8cs90cEAjH0iW F/1UmYrv viExhgKPZHmjD+5nY5oPLSASgGjrVqDS82BXxlS6jcqqBC74uDo8DunGvCX3n3qiEydmLmrZysM5lnvwudAR5OpAR9b1dfdeb006dF2EmpVYDHca3jR9mInRIjXKV6DZL5ZM5EKUCr4LMx0yeJqWv16c0iWBrRb4Tiz7W5kSUDznW2c4OpveViD+hECLVp2KqWWMxBqHBmas5/Q5ptrZdd2K+UrYalG1ogPW6AOeqnpoY8aqjzZJl3BKNjw0KTCKyKMnTJmuq4w87vKGQDk4tXQkGrl8I1CbreCUAEBXl953JQlM= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Add set_ptes(), update_mmu_cache_range() and flush_dcache_folio(). Change the PG_dcache_clean flag from being per-page to per-folio. Signed-off-by: Matthew Wilcox (Oracle) Reviewed-by: Catalin Marinas Acked-by: Mike Rapoport (IBM) Cc: linux-arm-kernel@lists.infradead.org --- arch/arm64/include/asm/cacheflush.h | 4 +++- arch/arm64/include/asm/pgtable.h | 26 +++++++++++++++------ arch/arm64/mm/flush.c | 36 +++++++++++------------------ 3 files changed, 36 insertions(+), 30 deletions(-) diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h index 37185e978aeb..d115451ed263 100644 --- a/arch/arm64/include/asm/cacheflush.h +++ b/arch/arm64/include/asm/cacheflush.h @@ -114,7 +114,7 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *, #define copy_to_user_page copy_to_user_page /* - * flush_dcache_page is used when the kernel has written to the page + * flush_dcache_folio is used when the kernel has written to the page * cache page at virtual address page->virtual. * * If this page isn't mapped (ie, page_mapping == NULL), or it might @@ -127,6 +127,8 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *, */ #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 extern void flush_dcache_page(struct page *); +void flush_dcache_folio(struct folio *); +#define flush_dcache_folio flush_dcache_folio static __always_inline void icache_inval_all_pou(void) { diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 445b18d7a47c..76bba654b5d7 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -345,12 +345,21 @@ static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, set_pte(ptep, pte); } -static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, - pte_t *ptep, pte_t pte) -{ - page_table_check_ptes_set(mm, ptep, pte, 1); - return __set_pte_at(mm, addr, ptep, pte); +static inline void set_ptes(struct mm_struct *mm, unsigned long addr, + pte_t *ptep, pte_t pte, unsigned int nr) +{ + page_table_check_ptes_set(mm, ptep, pte, nr); + + for (;;) { + __set_pte_at(mm, addr, ptep, pte); + if (--nr == 0) + break; + ptep++; + addr += PAGE_SIZE; + pte_val(pte) += PAGE_SIZE; + } } +#define set_ptes set_ptes /* * Huge pte definitions. @@ -1049,8 +1058,9 @@ static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio) /* * On AArch64, the cache coherency is handled via the set_pte_at() function. */ -static inline void update_mmu_cache(struct vm_area_struct *vma, - unsigned long addr, pte_t *ptep) +static inline void update_mmu_cache_range(struct vm_fault *vmf, + struct vm_area_struct *vma, unsigned long addr, pte_t *ptep, + unsigned int nr) { /* * We don't do anything here, so there's a very small chance of @@ -1059,6 +1069,8 @@ static inline void update_mmu_cache(struct vm_area_struct *vma, */ } +#define update_mmu_cache(vma, addr, ptep) \ + update_mmu_cache_range(NULL, vma, addr, ptep, 1) #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) #ifdef CONFIG_ARM64_PA_BITS_52 diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c index 4e6476094952..013eead9b695 100644 --- a/arch/arm64/mm/flush.c +++ b/arch/arm64/mm/flush.c @@ -51,20 +51,13 @@ void copy_to_user_page(struct vm_area_struct *vma, struct page *page, void __sync_icache_dcache(pte_t pte) { - struct page *page = pte_page(pte); + struct folio *folio = page_folio(pte_page(pte)); - /* - * HugeTLB pages are always fully mapped, so only setting head page's - * PG_dcache_clean flag is enough. - */ - if (PageHuge(page)) - page = compound_head(page); - - if (!test_bit(PG_dcache_clean, &page->flags)) { - sync_icache_aliases((unsigned long)page_address(page), - (unsigned long)page_address(page) + - page_size(page)); - set_bit(PG_dcache_clean, &page->flags); + if (!test_bit(PG_dcache_clean, &folio->flags)) { + sync_icache_aliases((unsigned long)folio_address(folio), + (unsigned long)folio_address(folio) + + folio_size(folio)); + set_bit(PG_dcache_clean, &folio->flags); } } EXPORT_SYMBOL_GPL(__sync_icache_dcache); @@ -74,17 +67,16 @@ EXPORT_SYMBOL_GPL(__sync_icache_dcache); * it as dirty for later flushing when mapped in user space (if executable, * see __sync_icache_dcache). */ -void flush_dcache_page(struct page *page) +void flush_dcache_folio(struct folio *folio) { - /* - * HugeTLB pages are always fully mapped and only head page will be - * set PG_dcache_clean (see comments in __sync_icache_dcache()). - */ - if (PageHuge(page)) - page = compound_head(page); + if (test_bit(PG_dcache_clean, &folio->flags)) + clear_bit(PG_dcache_clean, &folio->flags); +} +EXPORT_SYMBOL(flush_dcache_folio); - if (test_bit(PG_dcache_clean, &page->flags)) - clear_bit(PG_dcache_clean, &page->flags); +void flush_dcache_page(struct page *page) +{ + flush_dcache_folio(page_folio(page)); } EXPORT_SYMBOL(flush_dcache_page);