From patchwork Mon Oct 16 10:14:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kartik X-Patchwork-Id: 13422920 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A1D5CDB465 for ; Mon, 16 Oct 2023 10:15:55 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id C256B8D005B; Mon, 16 Oct 2023 06:15:54 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id BB2838D005C; Mon, 16 Oct 2023 06:15:54 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id A03658D005B; Mon, 16 Oct 2023 06:15:54 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0010.hostedemail.com [216.40.44.10]) by kanga.kvack.org (Postfix) with ESMTP id 878858D0001 for ; Mon, 16 Oct 2023 06:15:54 -0400 (EDT) Received: from smtpin28.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay06.hostedemail.com (Postfix) with ESMTP id 4DFE2B5E02 for ; Mon, 16 Oct 2023 10:15:54 +0000 (UTC) X-FDA: 81350918628.28.52E9DC0 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2050.outbound.protection.outlook.com [40.107.94.50]) by imf01.hostedemail.com (Postfix) with ESMTP id 537A54000F for ; Mon, 16 Oct 2023 10:15:51 +0000 (UTC) Authentication-Results: imf01.hostedemail.com; dkim=pass header.d=Nvidia.com header.s=selector2 header.b=tHd0OC60; dmarc=pass (policy=reject) header.from=nvidia.com; spf=pass (imf01.hostedemail.com: domain of kkartik@nvidia.com designates 40.107.94.50 as permitted sender) smtp.mailfrom=kkartik@nvidia.com; arc=pass ("microsoft.com:s=arcselector9901:i=1") ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1697451351; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=vnCLkKiG3WoNwvXMTh+9d4u1aDhdbcmtKjbLuTY7D9k=; b=K1e82LUaQHQZtzJeXcqudOZprR5c/GsBIT16ZJ2sNNk185DgOO4+Kqcw/VT4DtocASJkGO G/4wDn7zLZGaKuszo3/M4zEtNPmzidxoGTWU5qxhDp28ZwG2OnLmd1RDbXGn4mdtSa8Qr5 2VdEzlTv397KW3RV7b4QaaZ8lc/cmRk= ARC-Authentication-Results: i=2; imf01.hostedemail.com; dkim=pass header.d=Nvidia.com header.s=selector2 header.b=tHd0OC60; dmarc=pass (policy=reject) header.from=nvidia.com; spf=pass (imf01.hostedemail.com: domain of kkartik@nvidia.com designates 40.107.94.50 as permitted sender) smtp.mailfrom=kkartik@nvidia.com; arc=pass ("microsoft.com:s=arcselector9901:i=1") ARC-Seal: i=2; s=arc-20220608; d=hostedemail.com; t=1697451351; a=rsa-sha256; cv=pass; b=mu7EQhiqhcFa71ChOL4wUSgPT4fbksx81+fu0gzTtU5lnRKL0H6sTQo0RDr6GLnRmEdAUU j2iXkNMaVNv2X40NVKpfj133LAhHY4JA+wTn1F9E9bbsfUsWU5P1LpO3vhsuKTgi/Kxjx1 N8aFu2JNZMd+dgUG2cQnTTE1Vlj4Qnw= ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=I/2MZ6FdFOw7AM5lE2jSam/dD/SDRm3UWLSgK9cSY59Hw6g+SAh5DRSg+IdMPPAPabJkXTLr0hlv6PtyIogH9I5nrHK8MqoVNnk9maN7L/vaRwvzIM1LTsSODsO7YCmHbSprhOobOJOy1Ha984y0iWXRCnAMjAOxkeAbpWJH6L0ngVwNscwLYFbn9NH7COcf92Ho6+6wl7GSSLtPrwRqvCNi9RqkMW4gc33dR/IYyJH1IzlzcZ2u7XbJ96F2peQF3Q1vlqnmkq/JxvihIxb6zVpykDOKw8uqgxH14+X4OUrLwxBKMMe/f/DN/7+ZGBR/5ordIUORXwTtMzS/pNUfaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=vnCLkKiG3WoNwvXMTh+9d4u1aDhdbcmtKjbLuTY7D9k=; b=OZ5flYqwDa/8sSbjkh5fOnGr4CnUrVFI6jSx2Njt8Vj+q4ytFXcQTzcVfFAK9/wnFDqR9Yey9h4ktSdM9I5Rf91fbqxktd2qQ92QRh0Ac8CkRBt/jhmBoo+SJ6EB5543lclH4kmpCxphUAGD56ENAx+69E0eYArMq6tkfkTrM8bh4pMvLTfedxVO6PQiewOq9jJ9XLG7oXKBLfEVso9d5CghW1JzKmlfHMFnku0O9n+/rMEt82X2C97KCYZ6wiC2LFbcuRp2ozo2w5xoTFKDGps1DG6isDgITmlCjS01745ufVvQniqk3uVOctrLPUFdrXjWCtSZ9Zh48WNkZNyy7w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=gmail.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=vnCLkKiG3WoNwvXMTh+9d4u1aDhdbcmtKjbLuTY7D9k=; b=tHd0OC60KHVezR1q/NyJVSMSvNuDQpHZ08ykri3DrJ6UOuQz785KPImKGV8OLyZXp8CUSFmC5omrbk16etiEpljljE0xsH+MBfFtsYWZ6h6mK8mbj6MEkuQLDPvHkvOIGVEIyrb/Wo2XDqHPzL5oq/2tex1GEgAzB+Tg1Ikt8v1U9Bl8x4vKLeW7wj4rl8ufky7mamgOfSP8ffyViNm4jlbnTUPBJIjJ+nNwaTFIn54xEjWIN9ulTP18beImHjsRKnMb2MCmkLBLOGy8Sm7djIRwTdrffnCTJ6hkHi3mUR8EK0r+uGIrKXG9luYRx1y9iU/9FATHr806vGTmX2ehDw== Received: from SA9PR10CA0014.namprd10.prod.outlook.com (2603:10b6:806:a7::19) by MW3PR12MB4508.namprd12.prod.outlook.com (2603:10b6:303:5b::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6886.36; Mon, 16 Oct 2023 10:15:47 +0000 Received: from SA2PEPF000015C8.namprd03.prod.outlook.com (2603:10b6:806:a7:cafe::18) by SA9PR10CA0014.outlook.office365.com (2603:10b6:806:a7::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6886.35 via Frontend Transport; Mon, 16 Oct 2023 10:15:47 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by SA2PEPF000015C8.mail.protection.outlook.com (10.167.241.198) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.22 via Frontend Transport; Mon, 16 Oct 2023 10:15:47 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 16 Oct 2023 03:15:30 -0700 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 16 Oct 2023 03:15:29 -0700 Received: from localhost.localdomain (10.127.8.10) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.986.41 via Frontend Transport; Mon, 16 Oct 2023 03:15:24 -0700 From: Kartik To: , , , , , , , , , , , , , , , , , , Subject: [PATCH v6 7/8] soc/tegra: fuse: Add ACPI support for Tegra194 and Tegra234 Date: Mon, 16 Oct 2023 15:44:35 +0530 Message-ID: <20231016101436.7146-8-kkartik@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231016101436.7146-1-kkartik@nvidia.com> References: <20231016101436.7146-1-kkartik@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C8:EE_|MW3PR12MB4508:EE_ X-MS-Office365-Filtering-Correlation-Id: 6c74d648-26f5-4277-33eb-08dbce30dda5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: DAJ48sWstUPNxt8Uo7a0vtRBzyzVJY4eYZ7ly+Qnndmu46Rh1A3SLW7Avsut8dE5oBQGKDBmq6wgnSwjDnOVQVLjf0ahkFdAKWws1Bt6zHlGsBnBCdcbKXaUfyQgo50S8w+bm1PILl0dkpzrXJhFw8RD5hiHIq4Qu9UAT1/DA9CGn8aJPHG5htrKtjgXEkICeOcy3VjsbDUcqbLPQfwsOA3qUZQHuH44pk69iXwUt+Ill/mA5pUdY39fz3xGruquG3o5psgVcLUwLj2IeptmX26nZ7D4Jl3H05+pypljLumpbUpW8lazA1FGLtySMMVPkN0RjoVVFaz4utecA0Uiqmp5QSZBhdXWEV/pdsCPSCPgLfsDek8ES9I47jpuZjDuu7OzZXC5D5d+V3IuBGMjIF2PO1EvCoYxxFpZTGbhg40BMdAz2n50IgSub6v2Vls6pVP8z1w2Y1Ar4ZgDsu7hZWHZLVOziu7fT3TIqutc3tt7VBNjD6o4PbjTNUe1z8MMqOAOYkRUKeTsaQvFrQMdLTuRoPhw3XkP09kkD7h7UxxTXQsrZxuIhLV/u1cslu1J8JiBYCGckUOFuGOFKTTben4xQ5yZNTvlOwmNOPiRcug2kkqh5IOCUZ4R9b2Ma5aH44/FeaELktKN3egs0NlGvFCPmu0iA9SDwoCTSAF3HixP38kBM9X9a+EFDqahljmXjaGi7OZUEvfpw98edH5EA5KwUX/0MBByQ69Q4mQtyJwfcEIlUheCDODgTtyZDqd1KDug69GGSOAz9Xh9x9wsks3g6B9rsI/3FrVDjdzVG1Nts2VrO5aOMXkYGova6jbb X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(396003)(39860400002)(346002)(376002)(136003)(230922051799003)(64100799003)(1800799009)(82310400011)(451199024)(186009)(36840700001)(40470700004)(46966006)(110136005)(478600001)(6666004)(70206006)(70586007)(26005)(1076003)(2616005)(426003)(316002)(86362001)(336012)(8676002)(8936002)(7416002)(2906002)(5660300002)(41300700001)(36756003)(7636003)(921005)(47076005)(356005)(36860700001)(83380400001)(82740400003)(40460700003)(40480700001)(83996005)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2023 10:15:47.3994 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6c74d648-26f5-4277-33eb-08dbce30dda5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C8.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4508 X-Rspamd-Queue-Id: 537A54000F X-Rspam-User: X-Rspamd-Server: rspam02 X-Stat-Signature: efhkmtw931phfds731aedbb74796ya9j X-HE-Tag: 1697451351-361865 X-HE-Meta: U2FsdGVkX18UsT51yrDMH//xkiVD/8HS4pWiYNaESzVfcIB8T65Wg1I1r0nrRY/F912KiB7wP1EjE3JwpqQG14n0wwBhkst9uwdB4y8FPs7QjFdesP8IAYYEZh/MBak4s+TADtmVQ+MILbizwdfpYFP3TmLhOkV625/LjkNBdKU9Kajfm7byx3BfKEbD9UfLKAwI60MfUzOjx0Vo7aPRwLQWrIRaMeII7xs+nJNqcHyOclMDs40+vgUjU1kvQtNNZ6eZW6PLsq9TgoeOPcZrZzm1Z+C4+ZXwQKKlTsaa3Rqu7tOA40ndabbQkRmn0olKfZbzJs/t+IabJ7Zs7m05tekoN/KfIblSDP+LG1SmfKttHOGUqqzx3EPPaQa7N1DUMrbLaAIFIlgvTzFXxaQ2HFbgqbdkvbyNMWpU5yYrAYu9pK99QdrZig4jdM8WNKVI2dddIa8JF8BXqXcnGQZkXOZ/C0umFOgw/HrD+M7knnObG2wim0Wj1EY0mwgr3IW0UAEkkqrNedvyRISfCXAbRHnN5ccsFVk8lIVn4C2aPKM4abjSpzm9wic/RhCnUzPf4lqhqNz5ZV2a+cwDz59bZpO4QQynoWoG7tGZaeniApfbkYqL89MIBgxmLIyxRKKjw+qDVWcDzOq1lTX4zgHUyRl42sJ6rUeGmu+J4/kn787moEPLpTa4G/cPnvY7MRkzxFDYZHxmxsPlO7FYsMeW5ERTOVCJ0/pCOt+Cb4QbSIIiFjrFTnRBbBOFK3J0ECUEFh7T4wW9yiiHLSHTGbD9Gh/aPLkTvQbbAiS0Jmca3RBogGO0CJStYNiIsCEPKU80q5EAvVb2wQ0TNLZcutexz+JWD0LvyurvIVvEPpdWcVRCXm3X4rIlOatIQbYesBLwHsFxAmeQL0A6k0xsS5Thob3wvsx3o0i1plhfhWdcIGxQ9Ear/v584NsZUqqy4GrNh8HGok3c4PMtRK+KZZ4 8MMCX5BN eM8qjSBsdufOWrlXczKjejIEZKK8oVDKC4RpDaJ/cZ0O9JEW+11mX7nlGtYEnKyvIB3K86ZNPpSwb4Y1k1gh/jE6bTV+mXP71KJhmOcEqG/ELoeqWLzIcKKITlbFUsIz4Gwt7WlpwlbwPQrayeMBWzcrDNLXiuzB2ehJrTdOefiex7zqWkkg3tZH0O1V2uBWgltNfxXr0ZjPeLAkhw4lXpn4JLe4C7gacGN1S0sSpDCaEeLtLW0vqFdlsQcfOL41SABcicvznYgWbFQKKq6/HPR9Po5pBbvJtSEHZDBd5TbstDnL+3OepItV502mY2znSZSZt1zhfJFA+ISB+n9zrlA+N4T4xqLr1BZQj5wR0qUbRHVbPux+lFcTrOekk03lm3Cx6U+1bruhglj0= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Add ACPI support for Tegra194 & Tegra243 SoC's. This requires following modifications to the probe when ACPI boot is used: - Initialize soc data. - Add nvmem lookups. - Register soc device. - use devm_clk_get_optional() instead of devm_clk_get() to get fuse->clk, as fuse clocks are not required when using ACPI boot. Also, drop '__init' keyword for tegra_soc_device_register() as this is also used by tegra_fuse_probe() and use dev_err_probe() wherever applicable. Signed-off-by: Kartik --- v4 -> v5: * Fix build warnings seen with tegra_fuse_acpi_match when CONFIG_ACPI is disabled. v3 -> v4: * Use dev_fwnode() to dereference the fwnode. * Add MODULE_DEVICE_TABLE for tegra_fuse_acpi_match. * Moved tegra_fuse_acpi_match above tegra_fuse_driver i.e., close to the user of tegra_fuse_acpi_match. * Moved the improvements made to fuse clk/rst get error handling to separate patch. * Moved ACPI related initialization after fuse->base is initialized in tegra_fuse_probe(), as this triggers a warning in tegra_fuse_read_early() which is called from fuse->soc->init(). v2 -> v3: * Updated commit message to specify changes related to inclusion of dev_err_probe(). v1 -> v2: * Updated ACPI ID table 'tegra_fuse_acpi_match'. * Removed ',' after "{ /* sentinel */ }" in 'tegra_fuse_acpi_match'. * Using same probe for ACPI and device-tree boot. * Added code for required initialization when ACPI boot is used. * Make clocks optional for ACPI. * Use dev_err_probe() wherever applicable. * Check if clock has been initialized only when device-tree boot is used. --- drivers/soc/tegra/fuse/fuse-tegra.c | 52 +++++++++++++++++++++++++++-- 1 file changed, 49 insertions(+), 3 deletions(-) diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c index 7a93c6512f7b..39a59545c93f 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c @@ -3,11 +3,13 @@ * Copyright (c) 2013-2023, NVIDIA CORPORATION. All rights reserved. */ +#include #include #include #include #include #include +#include #include #include #include @@ -152,7 +154,38 @@ static int tegra_fuse_probe(struct platform_device *pdev) return PTR_ERR(fuse->base); fuse->phys = res->start; - fuse->clk = devm_clk_get(&pdev->dev, "fuse"); + /* Initialize the soc data and lookups if using ACPI boot. */ + if (is_acpi_node(dev_fwnode(&pdev->dev)) && !fuse->soc) { + u8 chip; + + tegra_acpi_init_apbmisc(); + + chip = tegra_get_chip_id(); + switch (chip) { +#if defined(CONFIG_ARCH_TEGRA_194_SOC) + case TEGRA194: + fuse->soc = &tegra194_fuse_soc; + break; +#endif +#if defined(CONFIG_ARCH_TEGRA_234_SOC) + case TEGRA234: + fuse->soc = &tegra234_fuse_soc; + break; +#endif + default: + return dev_err_probe(&pdev->dev, -EINVAL, "Unsupported SoC: %02x\n", chip); + } + + fuse->soc->init(fuse); + tegra_fuse_print_sku_info(&tegra_sku_info); + tegra_soc_device_register(); + + err = tegra_fuse_add_lookups(fuse); + if (err) + return dev_err_probe(&pdev->dev, err, "failed to add FUSE lookups\n"); + } + + fuse->clk = devm_clk_get_optional(&pdev->dev, "fuse"); if (IS_ERR(fuse->clk)) return dev_err_probe(&pdev->dev, PTR_ERR(fuse->clk), "failed to get FUSE clock\n"); @@ -275,10 +308,17 @@ static const struct dev_pm_ops tegra_fuse_pm = { SET_SYSTEM_SLEEP_PM_OPS(tegra_fuse_suspend, tegra_fuse_resume) }; +static const struct acpi_device_id __maybe_unused tegra_fuse_acpi_match[] = { + { "NVDA200F" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(acpi, tegra_fuse_acpi_match); + static struct platform_driver tegra_fuse_driver = { .driver = { .name = "tegra-fuse", .of_match_table = tegra_fuse_match, + .acpi_match_table = ACPI_PTR(tegra_fuse_acpi_match), .pm = &tegra_fuse_pm, .suppress_bind_attrs = true, }, @@ -300,7 +340,13 @@ u32 __init tegra_fuse_read_early(unsigned int offset) int tegra_fuse_readl(unsigned long offset, u32 *value) { - if (!fuse->read || !fuse->clk) + /* + * Wait for fuse->clk to be initialized if device-tree boot is used. + */ + if (is_of_node(dev_fwnode(fuse->dev)) && !fuse->clk) + return -EPROBE_DEFER; + + if (!fuse->read) return -EPROBE_DEFER; if (IS_ERR(fuse->clk)) @@ -383,7 +429,7 @@ const struct attribute_group tegra194_soc_attr_group = { }; #endif -struct device * __init tegra_soc_device_register(void) +struct device *tegra_soc_device_register(void) { struct soc_device_attribute *attr; struct soc_device *dev;