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shr@devkernel.io, deller@gmx.de, omosnace@redhat.com, ojeda@kernel.org, jhubbard@nvidia.com Subject: [PATCH v2 05/27] riscv: zicfiss/zicfilp extension csr and bit definitions Date: Thu, 28 Mar 2024 21:44:37 -0700 Message-Id: <20240329044459.3990638-6-debug@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240329044459.3990638-1-debug@rivosinc.com> References: <20240329044459.3990638-1-debug@rivosinc.com> MIME-Version: 1.0 X-Stat-Signature: 7ikpm9u1ip64gchhi1drbeixftrd57e5 X-Rspamd-Server: rspam10 X-Rspamd-Queue-Id: 736EB120017 X-Rspam-User: X-HE-Tag: 1711687565-890271 X-HE-Meta: U2FsdGVkX18prR9jrLo15pRI6t4poVWyoX8W+XLktBov5JAbGu1akAO2FBNHZEDVTgC+xWFa7Nbskl8uIhs7ahSyzvBWF1Csqcxiy/6b7donN8B2vxJIMcbNc8y1K7nYM3kdrnbgFA2J0P5dX9YbYimvUcGKjb/o3mOLEvYyv2Jh3I7Qs1AhqgGMd2dxY6NQ7oAlio0S0QHpAjmYesrLXeIHM4+rspBDJx5/CQodEjUmDUfioYoFPadCkx71eBV0rt8Y5hLF50HQKt76M9kmzL7hQiI9W+nryy9KI+1PKKRT+Z79qo519IsSFbx5cmllyJhTC2B7SdT/2pziW8qu9Jhrtu8X0qmtbydGQuqiVqlSxFydgRrzuucTCp6wdR29GflbKfIkCYx0OLKip3wvg+/fbWhymXSvEPE9z+cbjLL8IRP1KLIpoR6QWITN1UkSv/Ap5h1m/BW7EHzP1R/kwJWMtVzN1Rjhl6C3BuzLaXgqyC0eULV6HX5nt2UADqq5PuSaI+IoIVUZhSBoVh8NW8n2+hGmI8AWiDn7o+GhUb6YkEYIJ2ZO74g9SSkz2yD9PK8QTHYOkf3s5MQ/1Nw7r8tNrQuSO/byjAdZRLCTbHXpwgtKU3J1AmGkXp4eIyMR1107KFrjq8c/BRBLtmCbUK5j4b7ZPE4RmabKCgK4yA8twz9G/i17/oyq3E5moZuUv74hCuTYkscFQLYiMVaJCf59or0kMoQATaVYkdEPNmTalz1CiVj4NpLcrWoxwSSHQ846FUwqYJsbW2aTprVH1xB6fozJHtyIsDfHin5iYq5OYom2+yIYQ+c26gYoq6k2F5tm+oxkRkWhyC2z1t/yGO67F4gRqjZ51o/JNgzUmqwb9aNIMbk2SbMHrA9ciM+A2IyebiOj4NDjJLcB7FPwOET5mkx2Rh7Ha/jhTWVvFP3xE44rQLhK7rUrWTVsNCmHJ4BK6xn3IcR4atbJRk+ O7E+bs77 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A trap or interrupt can occur between an indirect jmp/call and target instr. `expected landing pad` bit from CPU is recorded into xstatus CSR so that when supervisor performs xret, `expected landing pad` state of CPU can be restored. zicfiss adds one new CSR - CSR_SSP: CSR_SSP contains current shadow stack pointer. Signed-off-by: Deepak Gupta --- arch/riscv/include/asm/csr.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index bbd2207adb39..3bb126d1c5ff 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -18,6 +18,15 @@ #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ +/* zicfilp landing pad status bit */ +#define SR_SPELP _AC(0x00800000, UL) +#define SR_MPELP _AC(0x020000000000, UL) +#ifdef CONFIG_RISCV_M_MODE +#define SR_ELP SR_MPELP +#else +#define SR_ELP SR_SPELP +#endif + #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ #define SR_FS_OFF _AC(0x00000000, UL) #define SR_FS_INITIAL _AC(0x00002000, UL) @@ -196,6 +205,8 @@ #define ENVCFG_PBMTE (_AC(1, ULL) << 62) #define ENVCFG_CBZE (_AC(1, UL) << 7) #define ENVCFG_CBCFE (_AC(1, UL) << 6) +#define ENVCFG_LPE (_AC(1, UL) << 2) +#define ENVCFG_SSE (_AC(1, UL) << 3) #define ENVCFG_CBIE_SHIFT 4 #define ENVCFG_CBIE (_AC(0x3, UL) << ENVCFG_CBIE_SHIFT) #define ENVCFG_CBIE_ILL _AC(0x0, UL) @@ -216,6 +227,11 @@ #define SMSTATEEN0_HSENVCFG (_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT) #define SMSTATEEN0_SSTATEEN0_SHIFT 63 #define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT) +/* + * zicfiss user mode csr + * CSR_SSP holds current shadow stack pointer. + */ +#define CSR_SSP 0x011 /* symbolic CSR names: */ #define CSR_CYCLE 0xc00