From patchwork Tue Apr 2 00:17:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ho-Ren (Jack) Chuang" X-Patchwork-Id: 13613187 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89880CD1292 for ; Tue, 2 Apr 2024 00:17:49 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 67A306B00A1; Mon, 1 Apr 2024 20:17:48 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 62A706B00A2; Mon, 1 Apr 2024 20:17:48 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 42F986B00A3; Mon, 1 Apr 2024 20:17:48 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0015.hostedemail.com [216.40.44.15]) by kanga.kvack.org (Postfix) with ESMTP id 1CFCA6B00A1 for ; Mon, 1 Apr 2024 20:17:48 -0400 (EDT) Received: from smtpin06.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay07.hostedemail.com (Postfix) with ESMTP id ABAF2160866 for ; Tue, 2 Apr 2024 00:17:47 +0000 (UTC) X-FDA: 81962678574.06.F29C467 Received: from mail-qt1-f172.google.com (mail-qt1-f172.google.com [209.85.160.172]) by imf14.hostedemail.com (Postfix) with ESMTP id DBE36100002 for ; Tue, 2 Apr 2024 00:17:45 +0000 (UTC) Authentication-Results: imf14.hostedemail.com; dkim=pass header.d=bytedance.com header.s=google header.b=El0S2B6W; spf=pass (imf14.hostedemail.com: domain of horenchuang@bytedance.com designates 209.85.160.172 as permitted sender) smtp.mailfrom=horenchuang@bytedance.com; dmarc=pass (policy=quarantine) header.from=bytedance.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1712017065; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=PZYYFgVRrQCyHvtBEuYH7h6o9TH4NNMhZD/5GyRy63w=; b=0M16mttaQGlc2rzVFUySZSlcLjsm08smBmi1IaRn7ayZh8/Q32RMtC2wxLduhyOMsYwxCX 37pYoSEaO3t1+0JCiya9fkZCiblMcYlPOhEDrzkBNqd3vJ8v/ZHu6SUZ0oMVuE1z+kx8/A dNzu8OTTc+RyldwPJuO+OmgNvpPVV/I= ARC-Authentication-Results: i=1; imf14.hostedemail.com; dkim=pass header.d=bytedance.com header.s=google header.b=El0S2B6W; spf=pass (imf14.hostedemail.com: domain of horenchuang@bytedance.com designates 209.85.160.172 as permitted sender) smtp.mailfrom=horenchuang@bytedance.com; dmarc=pass (policy=quarantine) header.from=bytedance.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1712017065; a=rsa-sha256; cv=none; b=KoZY0zkCykesiNMsm6bDSY+bFi2BViqoPz+w7q+4PejnUGd3zG5F4m6rMwfT1OuPJiStrO c46s8SQ1aWqwUH1F5M7+zHK+VX1GshuRvSRNnGeYDlviMpCwOpE4hgeNwHFlpNhqhE10FL Zvzm0BF+xoLcM0lHbWw/QKUwJ/q/XKc= Received: by mail-qt1-f172.google.com with SMTP id d75a77b69052e-432b5b3dad7so25780461cf.0 for ; Mon, 01 Apr 2024 17:17:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bytedance.com; s=google; t=1712017065; x=1712621865; darn=kvack.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PZYYFgVRrQCyHvtBEuYH7h6o9TH4NNMhZD/5GyRy63w=; b=El0S2B6WVgLujrRsi/1ifPad6WqitxUC5pEAezoOCIdasHd3SMTtWgYTLWni4PKEq7 dR/hIFxtAi8af/Qvxch8JxPci6zfgF3nzoD17Shm+S9huaxvN9PU2KKh1ObeRT8VHyG/ pmyGF0o+yKAqK7spMRs0PTLUIzE0op0ggEr3DIbMeTu2Yczou8WV15ipuRwgW/eVHfzv qcthcHhJUkM7Hq75yZnA3ejPlwKJdiUKHCxvyOvDa1azUwB+PCMNQ/uFWTm856ZgraWx PEbctPNJ+zVrLREnFuGeEAwYZZxQEm6BfUJazwjKr31qbEZzzM988Djxi9X2Ui80F/0X 3zmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712017065; x=1712621865; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PZYYFgVRrQCyHvtBEuYH7h6o9TH4NNMhZD/5GyRy63w=; b=i8mSPdS9ro7RsFHDKlL1+xT/hPCIaqPcVbZFnK9noAxwWzWvz9BrG/gIOURQyv2Esw nX8rnqZh+hSAGcL34ReQbhh1UF4njVDc7D6ECEgtSeJLdJJg/COIskTPfXmKfpqhuB+m AZ/l9b5mjiU+OXP8t8Pw8N/FgXOrTqYPYOYIHWDo7DCl1Wu5aPMWreVKkDDP7++/T0yq qpflRQ8SdYfWTk4gznvyJwXfjxdA5UJD1JtXv7VHTcO4b6xFu+XI2e8bTySfH/jgpsDw sJoRYoZiQF+3R7RDag2LGuocVnQ+XKOi2lHwgx6zF/qJgWvN0LdK89/lOy1cWW0h8HOa i3ag== X-Forwarded-Encrypted: i=1; AJvYcCVCMx8BPr8JPneu4IYzOg3Vd6+A2uL3mdXPwzwqi/MUi2biI45MVF0AEoVdZlZVdehoM4BNzklD33agQGeQpJI2mIU= X-Gm-Message-State: AOJu0YwA69Yb1IORBlCssA20KNDJfQ8D62FTNZcjqSrsszwFBcDyrx4I EdoAdatZl0hhfmtH1N7VfF1bcGVtQA2gmIWo/iuXTfYljUcYSO0/UcmlG1SjyB4= X-Google-Smtp-Source: AGHT+IH0dKZtlTit1GSkvLXp6F0jF1c0z74lQPxxIbr4JWCWw37kSgbA6kdWs7YXSpceE6HdVzmoDA== X-Received: by 2002:ad4:4c46:0:b0:699:184a:9315 with SMTP id cs6-20020ad44c46000000b00699184a9315mr358028qvb.62.1712017064933; Mon, 01 Apr 2024 17:17:44 -0700 (PDT) Received: from n231-228-171.byted.org ([130.44.212.125]) by smtp.gmail.com with ESMTPSA id e10-20020a0562141d0a00b00698f9771822sm3013112qvd.83.2024.04.01.17.17.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Apr 2024 17:17:44 -0700 (PDT) From: "Ho-Ren (Jack) Chuang" To: "Huang, Ying" , "Gregory Price" , aneesh.kumar@linux.ibm.com, mhocko@suse.com, tj@kernel.org, john@jagalactic.com, "Eishan Mirakhur" , "Vinicius Tavares Petrucci" , "Ravis OpenSrc" , "Alistair Popple" , "Srinivasulu Thanneeru" , "SeongJae Park" , Dan Williams , Vishal Verma , Dave Jiang , Andrew Morton , nvdimm@lists.linux.dev, linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org Cc: "Ho-Ren (Jack) Chuang" , "Ho-Ren (Jack) Chuang" , "Ho-Ren (Jack) Chuang" , qemu-devel@nongnu.org, Hao Xiang Subject: [PATCH v10 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info Date: Tue, 2 Apr 2024 00:17:38 +0000 Message-Id: <20240402001739.2521623-3-horenchuang@bytedance.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20240402001739.2521623-1-horenchuang@bytedance.com> References: <20240402001739.2521623-1-horenchuang@bytedance.com> MIME-Version: 1.0 X-Rspamd-Queue-Id: DBE36100002 X-Rspam-User: X-Stat-Signature: bnmyjn757r7r5tripsww6bgpzo5u8maw X-Rspamd-Server: rspam01 X-HE-Tag: 1712017065-228187 X-HE-Meta: U2FsdGVkX19kk+fx82mRf3JpO8ow/ajejmIv64dMqJWz+2Ne3NmPZQHnpKqK2c2E19DHHNdGu9+qqGDuPkU069vGJyN2YmXhxfIj7yJudYPWDfJtgBxPIs1p/bxw7xKqCqHVlaAIPqdUIVtVJbLf7vYGWLbrO5xTXKJFGCNrPpxzEV3Mun0BBU0P0bi2eOLVu+FFQSwLZIfaVc5LgyytAN418b9HC/jRVLPx9qun9+ibJ+ghQnaWopZPXKg8dN99rcBIWkndnuH0s/wIYbFnT0nUKefstsWgq8lveP1DXBWzPaw/zmzgpRzfsexg9iJzDYNP+ltMnuwak4Ct2EOA6VIkJ6bOUKOHeq9BsmYl5jGIuMK5ZHRorBYvO607Rd3yOr2ZniKA/vtTSMG22RETP25UAw9EMfBdzXYpnLKbv1Cs4lehm966mgrkD+OM2KO88UzcH9Pi+Sb7hOlt/Flh3tHKLD8yzzkf1LvWJHJF0wWe2td8XDeNahLP4S2trQ08jjOyoEs+Ebgo65kgv6z2oCmq7fesHj9UR1v45YjPeS1BGR5wvgh0gAvnvC5q8HwRPoPwwMf6Kr4Fif5zMwTGI9raEnIWAYNxSD+ZaU8L4lKh/CudkhYuK42Lt7HpDmD1uPxuCzKkWkXTFNXLSQLJ7u3YTW3hL9k+FNLKDDYqkcXj+WIuylIRv2yb9mIQXmwb2tFEKw2HTAiuBdNZL0w1sM/18wbIep3J61ZIA8bVWCtc5hcPQyWNdHPsM92MIQ2Plu+5MYCQNxOEOdAhMtWwYP0XhroglYkTnSpv2B6FRX9r6rPE9/uo8/STM7bex7XK1QK/MmUbxodP8jMzZw8VcUHBRalQ2N9/Fe2xlKBHDRDbKSERoXdPyEltPpMj4n96IdQugs4QCDLGmbd/e6ZQky6uVV+UJccYKVQ1jUvm3Kb4+xljmGDiombuU5NiTZgCCDuie3KmoZcSMfGtajm 1O3rW+66 co1j9sMHQv5C2N3J6RuJwoF5CERLiYVkPFVgNHdVClYQHN/p2S0lN0zybt9d9Ti70INW6a/oBjLDmVA7uIVdp/Cxi1oM8iUI0CVUFSw6Hcsbz3MrG1ZYZhORBEdilO1hv5hXnsOIOqdXDSebtWVxQwPmUgU0Ap0REKSMGBIFl5uGyQjEgJ9JcmtxbAhR6ABXDnyPzFZNoSeICseLW6ldBLtMl6FhkvtfxbPLvnqrFvn9yurx4hrWAXKNrbroNwO9VEEAdWT2FFEXf4AB7rJlK6Jrls/671aPOqDsIBGhYRMmU3tdPK11xit1eRdjg4md100gApxFnwckIQEn4V2rXZrkloLIQoDlGbeA74bGs3ElALTxa3rDIUdsDZ+wQya2sxkEbe1PY7zJ0qIhJ2NvvVa2e8w2pMJAW32IsOPaYmC6ohQUq+U7DDzbqgOIWHOhryuFO+U5W05/Q0ZN99huW7JXyB2+1ZfGdkuPW4AqXejcHYOzqTqCqsAmhewA0ds6mir3Z X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: The current implementation treats emulated memory devices, such as CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory (E820_TYPE_RAM). However, these emulated devices have different characteristics than traditional DRAM, making it important to distinguish them. Thus, we modify the tiered memory initialization process to introduce a delay specifically for CPUless NUMA nodes. This delay ensures that the memory tier initialization for these nodes is deferred until HMAT information is obtained during the boot process. Finally, demotion tables are recalculated at the end. * late_initcall(memory_tier_late_init); Some device drivers may have initialized memory tiers between `memory_tier_init()` and `memory_tier_late_init()`, potentially bringing online memory nodes and configuring memory tiers. They should be excluded in the late init. * Handle cases where there is no HMAT when creating memory tiers There is a scenario where a CPUless node does not provide HMAT information. If no HMAT is specified, it falls back to using the default DRAM tier. * Introduce another new lock `default_dram_perf_lock` for adist calculation In the current implementation, iterating through CPUlist nodes requires holding the `memory_tier_lock`. However, `mt_calc_adistance()` will end up trying to acquire the same lock, leading to a potential deadlock. Therefore, we propose introducing a standalone `default_dram_perf_lock` to protect `default_dram_perf_*`. This approach not only avoids deadlock but also prevents holding a large lock simultaneously. * Upgrade `set_node_memory_tier` to support additional cases, including default DRAM, late CPUless, and hot-plugged initializations. To cover hot-plugged memory nodes, `mt_calc_adistance()` and `mt_find_alloc_memory_type()` are moved into `set_node_memory_tier()` to handle cases where memtype is not initialized and where HMAT information is available. * Introduce `default_memory_types` for those memory types that are not initialized by device drivers. Because late initialized memory and default DRAM memory need to be managed, a default memory type is created for storing all memory types that are not initialized by device drivers and as a fallback. Signed-off-by: Ho-Ren (Jack) Chuang Signed-off-by: Hao Xiang Reviewed-by: "Huang, Ying" --- include/linux/memory-tiers.h | 5 +- mm/memory-tiers.c | 95 +++++++++++++++++++++++++++++------- 2 files changed, 81 insertions(+), 19 deletions(-) diff --git a/include/linux/memory-tiers.h b/include/linux/memory-tiers.h index a44c03c2ba3a..16769552a338 100644 --- a/include/linux/memory-tiers.h +++ b/include/linux/memory-tiers.h @@ -140,12 +140,13 @@ static inline int mt_perf_to_adistance(struct access_coordinate *perf, int *adis return -EIO; } -struct memory_dev_type *mt_find_alloc_memory_type(int adist, struct list_head *memory_types) +static inline struct memory_dev_type *mt_find_alloc_memory_type(int adist, + struct list_head *memory_types) { return NULL; } -void mt_put_memory_types(struct list_head *memory_types) +static inline void mt_put_memory_types(struct list_head *memory_types) { } diff --git a/mm/memory-tiers.c b/mm/memory-tiers.c index 974af10cfdd8..44fa10980d37 100644 --- a/mm/memory-tiers.c +++ b/mm/memory-tiers.c @@ -36,6 +36,11 @@ struct node_memory_type_map { static DEFINE_MUTEX(memory_tier_lock); static LIST_HEAD(memory_tiers); +/* + * The list is used to store all memory types that are not created + * by a device driver. + */ +static LIST_HEAD(default_memory_types); static struct node_memory_type_map node_memory_types[MAX_NUMNODES]; struct memory_dev_type *default_dram_type; @@ -108,6 +113,8 @@ static struct demotion_nodes *node_demotion __read_mostly; static BLOCKING_NOTIFIER_HEAD(mt_adistance_algorithms); +/* The lock is used to protect `default_dram_perf*` info and nid. */ +static DEFINE_MUTEX(default_dram_perf_lock); static bool default_dram_perf_error; static struct access_coordinate default_dram_perf; static int default_dram_perf_ref_nid = NUMA_NO_NODE; @@ -505,7 +512,8 @@ static inline void __init_node_memory_type(int node, struct memory_dev_type *mem static struct memory_tier *set_node_memory_tier(int node) { struct memory_tier *memtier; - struct memory_dev_type *memtype; + struct memory_dev_type *mtype = default_dram_type; + int adist = MEMTIER_ADISTANCE_DRAM; pg_data_t *pgdat = NODE_DATA(node); @@ -514,11 +522,20 @@ static struct memory_tier *set_node_memory_tier(int node) if (!node_state(node, N_MEMORY)) return ERR_PTR(-EINVAL); - __init_node_memory_type(node, default_dram_type); + mt_calc_adistance(node, &adist); + if (node_memory_types[node].memtype == NULL) { + mtype = mt_find_alloc_memory_type(adist, &default_memory_types); + if (IS_ERR(mtype)) { + mtype = default_dram_type; + pr_info("Failed to allocate a memory type. Fall back.\n"); + } + } + + __init_node_memory_type(node, mtype); - memtype = node_memory_types[node].memtype; - node_set(node, memtype->nodes); - memtier = find_create_memory_tier(memtype); + mtype = node_memory_types[node].memtype; + node_set(node, mtype->nodes); + memtier = find_create_memory_tier(mtype); if (!IS_ERR(memtier)) rcu_assign_pointer(pgdat->memtier, memtier); return memtier; @@ -655,6 +672,33 @@ void mt_put_memory_types(struct list_head *memory_types) } EXPORT_SYMBOL_GPL(mt_put_memory_types); +/* + * This is invoked via `late_initcall()` to initialize memory tiers for + * CPU-less memory nodes after driver initialization, which is + * expected to provide `adistance` algorithms. + */ +static int __init memory_tier_late_init(void) +{ + int nid; + + mutex_lock(&memory_tier_lock); + for_each_node_state(nid, N_MEMORY) + if (node_memory_types[nid].memtype == NULL) + /* + * Some device drivers may have initialized memory tiers + * between `memory_tier_init()` and `memory_tier_late_init()`, + * potentially bringing online memory nodes and + * configuring memory tiers. Exclude them here. + */ + set_node_memory_tier(nid); + + establish_demotion_targets(); + mutex_unlock(&memory_tier_lock); + + return 0; +} +late_initcall(memory_tier_late_init); + static void dump_hmem_attrs(struct access_coordinate *coord, const char *prefix) { pr_info( @@ -668,7 +712,7 @@ int mt_set_default_dram_perf(int nid, struct access_coordinate *perf, { int rc = 0; - mutex_lock(&memory_tier_lock); + mutex_lock(&default_dram_perf_lock); if (default_dram_perf_error) { rc = -EIO; goto out; @@ -716,23 +760,30 @@ int mt_set_default_dram_perf(int nid, struct access_coordinate *perf, } out: - mutex_unlock(&memory_tier_lock); + mutex_unlock(&default_dram_perf_lock); return rc; } int mt_perf_to_adistance(struct access_coordinate *perf, int *adist) { - if (default_dram_perf_error) - return -EIO; + int rc = 0; - if (default_dram_perf_ref_nid == NUMA_NO_NODE) - return -ENOENT; + mutex_lock(&default_dram_perf_lock); + if (default_dram_perf_error) { + rc = -EIO; + goto out; + } if (perf->read_latency + perf->write_latency == 0 || - perf->read_bandwidth + perf->write_bandwidth == 0) - return -EINVAL; + perf->read_bandwidth + perf->write_bandwidth == 0) { + rc = -EINVAL; + goto out; + } - mutex_lock(&memory_tier_lock); + if (default_dram_perf_ref_nid == NUMA_NO_NODE) { + rc = -ENOENT; + goto out; + } /* * The abstract distance of a memory node is in direct proportion to * its memory latency (read + write) and inversely proportional to its @@ -745,9 +796,10 @@ int mt_perf_to_adistance(struct access_coordinate *perf, int *adist) (default_dram_perf.read_latency + default_dram_perf.write_latency) * (default_dram_perf.read_bandwidth + default_dram_perf.write_bandwidth) / (perf->read_bandwidth + perf->write_bandwidth); - mutex_unlock(&memory_tier_lock); - return 0; +out: + mutex_unlock(&default_dram_perf_lock); + return rc; } EXPORT_SYMBOL_GPL(mt_perf_to_adistance); @@ -858,7 +910,8 @@ static int __init memory_tier_init(void) * For now we can have 4 faster memory tiers with smaller adistance * than default DRAM tier. */ - default_dram_type = alloc_memory_type(MEMTIER_ADISTANCE_DRAM); + default_dram_type = mt_find_alloc_memory_type(MEMTIER_ADISTANCE_DRAM, + &default_memory_types); if (IS_ERR(default_dram_type)) panic("%s() failed to allocate default DRAM tier\n", __func__); @@ -868,6 +921,14 @@ static int __init memory_tier_init(void) * types assigned. */ for_each_node_state(node, N_MEMORY) { + if (!node_state(node, N_CPU)) + /* + * Defer memory tier initialization on CPUless numa nodes. + * These will be initialized after firmware and devices are + * initialized. + */ + continue; + memtier = set_node_memory_tier(node); if (IS_ERR(memtier)) /*