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Tue, 16 Jul 2024 23:04:25 +0800 (CST) Received: from P_UKIT01-A7bmah.china.huawei.com (10.48.159.153) by lhrpeml500006.china.huawei.com (7.191.161.198) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Tue, 16 Jul 2024 16:04:23 +0100 From: To: , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [RFC PATCH v9 01/11] EDAC: Add generic EDAC RAS feature driver Date: Tue, 16 Jul 2024 16:03:25 +0100 Message-ID: <20240716150336.2042-2-shiju.jose@huawei.com> X-Mailer: git-send-email 2.43.0.windows.1 In-Reply-To: <20240716150336.2042-1-shiju.jose@huawei.com> References: <20240716150336.2042-1-shiju.jose@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.48.159.153] X-ClientProxiedBy: lhrpeml500005.china.huawei.com (7.191.163.240) To lhrpeml500006.china.huawei.com (7.191.161.198) X-Rspamd-Server: rspam11 X-Rspamd-Queue-Id: 8A8A1200BC X-Stat-Signature: r4noxnfnzodhutweqm7crnjdjww6o4em X-Rspam-User: X-HE-Tag: 1721142269-920422 X-HE-Meta: U2FsdGVkX19ytOCPKRwEdbPZBgv5qlEfWAWSbMbYZXxIY71oe3ubk/uNQQHeLeCv0GzSpw1QOSMBc4EsdQWpUOoTw5IhdcK5IerkxBZ4UbVqRJSYl/yJBmqvaEpLWxL1sIVRi5WFaqXGAeqsSHA56CEQaHMjkMgFWcvoznzCjUEN/iqMIuYXML3DkP+R+lWgPZgnzD/QExIE5s2j8KzXr/Pqt0YH0jUhjj8wxCAbr+cMt3uWwWhTJcTDLQ0GfJmPiVK/zwc6b8zTo/mRY/YRxx+EYap0rx2INjChWU19zi8B+1m7iQyt1bfqI1lZfnjeodsFzT0mq7wyDw71o2AEX1q5iUNQcOoOo54GlMvzelrDRoXhlUHPIkQEHlk3YH3zpOlHzHltEIf+8NDaCFxPlDDsdDG0roe9lNHFhqS133HCNYVWS9bLT1NTJMsI665yf3/dAEXoAsmoAhE0AVkQYhXmv+q9OuUICAX3nwOv0PD8E6KKHSUtvmm5w72ctaQ1qj28bO6XbBvxMObOvMR2Ed2X2g5yC1Rjc9tmPSCq5uyp9B4A0UeegCLGMXDjwOagAqjIu/R6S288ftKQKoYl2dhG+treY5X/vF+t+e3AjQAjYcbom4ZrrypI0me3lCyDwjJ4BLyuqdbgiZ3VZk/zF1UVL15t3TEGFAFb/dAkEhe65fmHxmugkg52JCqm6s3kyhSAhiSiZ2ZQjVlPs+Bb2hbg0Uotxg4w5KJtgqrayv5A9NuCvZg6p1ArY3LA69tHMN2BPbwjlSdj2crlnD719ZWXnDb+3NCG6/VHvq2NaKCAqYHoZCvArwMsmcZGy8vmyakFIcGFAtQjo1epOKXpkQsmbedm05RN/8urSJ1mDre/xcHo1ONR54bynfiFvpB9KyEJf3/ue9uUr3/qRqvBAE66FO/hnbqbOAfMiPMzVwxdJrziHDP0+Tcls0Pc0jpl8W3YxhjFChI4ZChwmXq r6qDKvO0 5sSSsa4zcJ1WLIccfowOorBTY5EFIdlMMOU9VR5obis0QzpDu7IzJpf/oGuAsbIf65SKLH5pcDY55Vxw3UL/GP0O0LwKfJLhcFijLmwfefVmxNYcj6T8dRG9zzKruQyLR3DyiCfesISf3/+jXTi+tG/n+EpJ2CP5FmCpGHOh0MDu/iel2avULQPr6vPUVIBY3dnmu9zjsgQrCMaHlg+kO4VcSjg== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: From: Shiju Jose Add generic EDAC driver supports registering RAS features supported in the system. The driver exposes feature's control attributes to the userspace in /sys/bus/edac/devices/// Co-developed-by: Jonathan Cameron Signed-off-by: Jonathan Cameron Signed-off-by: Shiju Jose --- drivers/edac/Makefile | 1 + drivers/edac/edac_ras_feature.c | 155 +++++++++++++++++++++++++++++++ include/linux/edac_ras_feature.h | 66 +++++++++++++ 3 files changed, 222 insertions(+) create mode 100755 drivers/edac/edac_ras_feature.c create mode 100755 include/linux/edac_ras_feature.h diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index 9c09893695b7..c532b57a6d8a 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_EDAC) := edac_core.o edac_core-y := edac_mc.o edac_device.o edac_mc_sysfs.o edac_core-y += edac_module.o edac_device_sysfs.o wq.o +edac_core-y += edac_ras_feature.o edac_core-$(CONFIG_EDAC_DEBUG) += debugfs.o diff --git a/drivers/edac/edac_ras_feature.c b/drivers/edac/edac_ras_feature.c new file mode 100755 index 000000000000..24a729fea66f --- /dev/null +++ b/drivers/edac/edac_ras_feature.c @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * EDAC RAS control feature driver supports registering RAS + * features with the EDAC and exposes the feature's control + * attributes to the userspace in sysfs. + * + * Copyright (c) 2024 HiSilicon Limited. + */ + +#define pr_fmt(fmt) "EDAC RAS CONTROL FEAT: " fmt + +#include + +static void edac_ras_dev_release(struct device *dev) +{ + struct edac_ras_feat_ctx *ctx = + container_of(dev, struct edac_ras_feat_ctx, dev); + + kfree(ctx); +} + +const struct device_type edac_ras_dev_type = { + .name = "edac_ras_dev", + .release = edac_ras_dev_release, +}; + +static void edac_ras_dev_unreg(void *data) +{ + device_unregister(data); +} + +static int edac_ras_feat_scrub_init(struct device *parent, + struct edac_scrub_data *sdata, + const struct edac_ras_feature *sfeat, + const struct attribute_group **attr_groups) +{ + sdata->ops = sfeat->scrub_ops; + sdata->private = sfeat->scrub_ctx; + + return 1; +} + +static int edac_ras_feat_ecs_init(struct device *parent, + struct edac_ecs_data *edata, + const struct edac_ras_feature *efeat, + const struct attribute_group **attr_groups) +{ + int num = efeat->ecs_info.num_media_frus; + + edata->ops = efeat->ecs_ops; + edata->private = efeat->ecs_ctx; + + return num; +} + +/** + * edac_ras_dev_register - register device for ras features with edac + * @parent: client device. + * @name: client device's name. + * @private: parent driver's data to store in the context if any. + * @num_features: number of ras features to register. + * @ras_features: list of ras features to register. + * + * Returns 0 on success, error otherwise. + * The new edac_ras_feat_ctx would be freed automatically. + */ +int edac_ras_dev_register(struct device *parent, char *name, + void *private, int num_features, + const struct edac_ras_feature *ras_features) +{ + const struct attribute_group **ras_attr_groups; + struct edac_ras_feat_ctx *ctx; + int attr_gcnt = 0; + int ret, feat; + + if (!parent || !name || !num_features || !ras_features) + return -EINVAL; + + ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->dev.parent = parent; + ctx->private = private; + + /* Double parse so we can make space for attributes */ + for (feat = 0; feat < num_features; feat++) { + switch (ras_features[feat].feat) { + case ras_feat_scrub: + attr_gcnt++; + break; + case ras_feat_ecs: + attr_gcnt += ras_features[feat].ecs_info.num_media_frus; + break; + default: + ret = -EINVAL; + goto ctx_free; + } + } + + ras_attr_groups = devm_kzalloc(parent, + (attr_gcnt + 1) * sizeof(*ras_attr_groups), + GFP_KERNEL); + if (!ras_attr_groups) { + ret = -ENOMEM; + goto ctx_free; + } + + attr_gcnt = 0; + for (feat = 0; feat < num_features; feat++, ras_features++) { + if (ras_features->feat == ras_feat_scrub) { + if (!ras_features->scrub_ops) + continue; + ret = edac_ras_feat_scrub_init(parent, &ctx->scrub, + ras_features, &ras_attr_groups[attr_gcnt]); + if (ret < 0) + goto ctx_free; + + attr_gcnt += ret; + } else if (ras_features->feat == ras_feat_ecs) { + if (!ras_features->ecs_ops) + continue; + ret = edac_ras_feat_ecs_init(parent, &ctx->ecs, + ras_features, &ras_attr_groups[attr_gcnt]); + if (ret < 0) + goto ctx_free; + + attr_gcnt += ret; + } else { + ret = -EINVAL; + goto ctx_free; + } + } + ras_attr_groups[attr_gcnt] = NULL; + ctx->dev.bus = edac_get_sysfs_subsys(); + ctx->dev.type = &edac_ras_dev_type; + ctx->dev.groups = ras_attr_groups; + dev_set_drvdata(&ctx->dev, ctx); + ret = dev_set_name(&ctx->dev, name); + if (ret) + goto ctx_free; + + ret = device_register(&ctx->dev); + if (ret) { + put_device(&ctx->dev); + return ret; + } + + return devm_add_action_or_reset(parent, edac_ras_dev_unreg, &ctx->dev); + +ctx_free: + kfree(ctx); + return ret; +} +EXPORT_SYMBOL_GPL(edac_ras_dev_register); diff --git a/include/linux/edac_ras_feature.h b/include/linux/edac_ras_feature.h new file mode 100755 index 000000000000..000e99141023 --- /dev/null +++ b/include/linux/edac_ras_feature.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * EDAC RAS control features. + * + * Copyright (c) 2024 HiSilicon Limited. + */ + +#ifndef __EDAC_RAS_FEAT_H +#define __EDAC_RAS_FEAT_H + +#include +#include + +#define EDAC_RAS_NAME_LEN 128 + +enum edac_ras_feat { + ras_feat_scrub, + ras_feat_ecs, + ras_feat_max +}; + +struct edac_ecs_ex_info { + u16 num_media_frus; +}; + +/* + * EDAC RAS feature information structure + */ +struct edac_scrub_data { + const struct edac_scrub_ops *ops; + void *private; +}; + +struct edac_ecs_data { + const struct edac_ecs_ops *ops; + void *private; +}; + +struct device; + +struct edac_ras_feat_ctx { + struct device dev; + void *private; + struct edac_scrub_data scrub; + struct edac_ecs_data ecs; +}; + +struct edac_ras_feature { + enum edac_ras_feat feat; + union { + const struct edac_scrub_ops *scrub_ops; + const struct edac_ecs_ops *ecs_ops; + }; + union { + struct edac_ecs_ex_info ecs_info; + }; + union { + void *scrub_ctx; + void *ecs_ctx; + }; +}; + +int edac_ras_dev_register(struct device *parent, char *dev_name, + void *parent_pvt_data, int num_features, + const struct edac_ras_feature *ras_features); +#endif /* __EDAC_RAS_FEAT_H */