From patchwork Thu Aug 1 12:06:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13750399 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB812C3DA64 for ; Thu, 1 Aug 2024 12:59:33 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 4395D8D0003; Thu, 1 Aug 2024 08:59:33 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 3C2218D0007; Thu, 1 Aug 2024 08:59:33 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 214808D0003; Thu, 1 Aug 2024 08:59:33 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0010.hostedemail.com [216.40.44.10]) by kanga.kvack.org (Postfix) with ESMTP id F15D56B0089 for ; Thu, 1 Aug 2024 08:59:32 -0400 (EDT) Received: from smtpin09.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay07.hostedemail.com (Postfix) with ESMTP id B41D9160D28 for ; Thu, 1 Aug 2024 12:59:32 +0000 (UTC) X-FDA: 82403682984.09.D39B192 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by imf02.hostedemail.com (Postfix) with ESMTP id D72CC80017 for ; Thu, 1 Aug 2024 12:59:30 +0000 (UTC) Authentication-Results: imf02.hostedemail.com; dkim=pass header.d=kernel.org header.s=k20201202 header.b=SGbG9HSU; spf=pass (imf02.hostedemail.com: domain of broonie@kernel.org designates 139.178.84.217 as permitted sender) smtp.mailfrom=broonie@kernel.org; dmarc=pass (policy=none) header.from=kernel.org ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1722517115; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=oe9Vexhwqj93GjpqzabS7C48jUF3MOTi7ueTZQ7hbvA=; b=ARv8L9oN9xg+igJpP0ggnyC+dOVuH/grWqiR3i2GVvGIggrmstyGCDZkoHTzTMYyGjlfq4 EorgYhH0TBC4gKSbuT8frK/HI4GYkq+aqLQxs8BZl5QnwMNRSx96xW0Tr36w7y0zj4bQ/f 2efjVE4J1UAqg1r7r7oG3u039OvVUxc= ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1722517115; a=rsa-sha256; cv=none; b=NYv7NI8AWLyfEFa4cSCHgeCtuPI47nIsduA7d1uQ/WfxlkEjtkZ9wrcIE45me2daebH6Mq ppM7UvsfMzriLOCrK5ibmUO0L/excXABy34ACQSn/e14XfN2/JigQw2e0FpxSOsD/eQNqA yfS/WB7e/XpObYo+i5MQTKwenarOe9U= ARC-Authentication-Results: i=1; imf02.hostedemail.com; dkim=pass header.d=kernel.org header.s=k20201202 header.b=SGbG9HSU; spf=pass (imf02.hostedemail.com: domain of broonie@kernel.org designates 139.178.84.217 as permitted sender) smtp.mailfrom=broonie@kernel.org; dmarc=pass (policy=none) header.from=kernel.org Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 0B8C762862; Thu, 1 Aug 2024 12:59:30 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 56BFBC4AF09; Thu, 1 Aug 2024 12:59:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722517169; bh=LJRx9dbx6SCHWemf1Wkonmx6LcV5PPBkBodAHDEcEts=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=SGbG9HSUe/7a3ExlPYPCv4L81giAZrIfuIgHOahyUE1y+liRYLKOTDH/4ugujV5AJ Yx9KGKXnA2zmSEKsdwrVWI2NMY4rzUgu15HBxTXtj74UADh8zMzoVoW+GPgoMlZ1HO IrSaWuThAnNJJ1K8GzlI0kjlG/NzuoGs0pObM6Ux0DZjFAtcf8fcroMamdazKixJBy EiuPtwWC6XiObL7ZxrkxvlRqJ7v+ujGC254EVqSoIkoa6TsiWq6PQuvOh21Fb7RNAu 4N6KNtWimUtC0eBrxxPnfb8sLYHPKDR5Qf9cad0Hxhvls7vo3O3fFuGI7RrO1NJkrb 2DXfG7dpJZ9CA== From: Mark Brown Date: Thu, 01 Aug 2024 13:06:46 +0100 Subject: [PATCH v10 19/40] arm64/gcs: Context switch GCS state for EL0 MIME-Version: 1.0 Message-Id: <20240801-arm64-gcs-v10-19-699e2bd2190b@kernel.org> References: <20240801-arm64-gcs-v10-0-699e2bd2190b@kernel.org> In-Reply-To: <20240801-arm64-gcs-v10-0-699e2bd2190b@kernel.org> To: Catalin Marinas , Will Deacon , Jonathan Corbet , Andrew Morton , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Arnd Bergmann , Oleg Nesterov , Eric Biederman , Shuah Khan , "Rick P. Edgecombe" , Deepak Gupta , Ard Biesheuvel , Szabolcs Nagy , Kees Cook Cc: "H.J. Lu" , Paul Walmsley , Palmer Dabbelt , Albert Ou , Florian Weimer , Christian Brauner , Thiago Jung Bauermann , Ross Burton , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Brown X-Mailer: b4 0.15-dev-37811 X-Developer-Signature: v=1; a=openpgp-sha256; l=6765; i=broonie@kernel.org; h=from:subject:message-id; bh=LJRx9dbx6SCHWemf1Wkonmx6LcV5PPBkBodAHDEcEts=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBmq4YU7fRD9Hg8vjWqmHFVnrRJhKG43A5c/5GNr8vv WGmGOmCJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZquGFAAKCRAk1otyXVSH0KgmB/ 4mAAl6dpDUJ+513JFxm8gMwmN8c/C3rsQdArwoDkfda+tiWMoZAvScNaIwibLzwvEJMxpldgs2RWql ueSBr2KKMOgrZsGWanCW7AIFQk1/kzHejFQnz5BxhONmn0RJ8vB21rfrW5KwiRm4OULvDyxc01RWNo DRR2/Q05gTaC0gwUwXDVii5ITTJE23qOA77TH3NS8OJiag+MCV7DFDuMRyxSN0mFdsO4yYoQMFc/ev NBtS2ZwBWiTB4hTZxJbfejjCHtV+APQUBwhPL8L77WHbYUIWRmNryLsCwiT3qM7PKSmRjecBlf+Pgz khi2R7Ve9atuRvFA3EjzSLTVDNrBxY X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-Rspamd-Queue-Id: D72CC80017 X-Stat-Signature: mcergf168fnw7fug7uxy5ksu9ccz1mng X-Rspamd-Server: rspam09 X-Rspam-User: X-HE-Tag: 1722517170-812565 X-HE-Meta: U2FsdGVkX1/bs6jibTQpnqUTjl+Awq4FNEbmBESRdFwZhH8gyMHxS9HRdFOLTnXVgt7Gb/9w7TjwV7Mj3ZG/U01+B2KbV/13y9iMU8KZdbItfuOQhcODHFSi/LD4zABLcfDKd868BfnFjCg5N/9ImjLkuV+yJ1M5zbaa0VjB25fXqB3ThY7aPgwOaPB3tMrJKQgq4mjNNRRNojwZmyN7g27WyLtuRxgE6+SInD6z85zRhL4jOpRLKztKmJ+IocDNlPPRJQSXNBMFAQOm7LIyRsxEEMxtTh6C/G2V5f3kbeKYVGZxveYDBSrxCHglusseSTQv2ulc3FSabBp6XpB+tRXQnbqP8HAkn61LP0vNqL7vgNhglj6hdtaxRpy/YrDgfhWF7ZId4AZUC/QhRdSv+abhMGV4Hh21Zir5vPz3oNEZyEwvsKq1RXOcHO4qkUKcYpYYFeSeucssTemXalkkjoMk4V9iGeeTXvjhGWQexuDijyOqNFlOiWCTLcooxe72DcLW08WmKqz1ihsNKAzoKhRJ5bogARzsFNAno007OXCUwK+8j6K/QgXhsv7ZrEQWQVvAlfc1Ln1dQOo7iJ62qBC8g8zKfjobcGDtuCnxiyAEEHnrNCXqhD34EtZdQVT572c/f7NNCZ5j84Glfpe4oZoxzeno58PBnWB1PborIsmf6o79g0FmSwuMc0+uBxyrfKMR0IMT54s5h22ddBoj7jPmHZluT3ThvoAASBrUTQLrS/8YzByHMwxXgYo9vCWIAWWGu7dy1H8pKe5KM4e0i11v/Rfvhia50sBmi/oyWcS/C9BTD0ptCfepJhpMuKl7HwfBPUCAm/TgzLQ4REajtt1Fl3PFb9duwHiS8fkaIbpWZTFab53OIAU+v3gyyhsgU5dG6f7DcEsDlkm0+5+zqHD4uyIrp3VdlkAH5l3zfwa+17isqfkVm5nW9MhqGLmaXHT1aic82fZcmaWdh4d EsDQKiN2 +Kdm5sRe3x4+eu+xnA8DaYvGPbjgzwmK3cCIOQUGFqRSeWRXoBVHu4ZGQpm0am4SEajNBNxt6Xv1vmnm9dXPLOmkKfgcIL6NZWc4kZb1vv9PeD4TM3uV4iawm22+xcbt5rhsML4ONRYeOzQNLCiwE5Q6+fN03jxR15PQGQX5c+ZqwlFdYyKJ5uUPfbyYHoSGcj0SPntH95jZmjHp/80x0xBkse/3H93Dy3AiJmfuCf/3OsfC7s934DwGRk//FxkvfGI1Czpr4c8yj3dz4wRec1yQ6JnJj6cluhcV/4cgsk9x4uMYbv3SVuhxcXsRuqaNOy4497illcerCpYPhAWmDky0vp9Kj31DKXCJYVjTr/7tCQEK6BPbNfdMzCLn24IUGlxlR X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: There are two registers controlling the GCS state of EL0, GCSPR_EL0 which is the current GCS pointer and GCSCRE0_EL1 which has enable bits for the specific GCS functionality enabled for EL0. Manage these on context switch and process lifetime events, GCS is reset on exec(). Also ensure that any changes to the GCS memory are visible to other PEs and that changes from other PEs are visible on this one by issuing a GCSB DSYNC when moving to or from a thread with GCS. Since the current GCS configuration of a thread will be visible to userspace we store the configuration in the format used with userspace and provide a helper which configures the system register as needed. On systems that support GCS we always allow access to GCSPR_EL0, this facilitates reporting of GCS faults if userspace implements disabling of GCS on error - the GCS can still be discovered and examined even if GCS has been disabled. Reviewed-by: Thiago Jung Bauermann Signed-off-by: Mark Brown --- arch/arm64/include/asm/gcs.h | 24 ++++++++++++++++ arch/arm64/include/asm/processor.h | 6 ++++ arch/arm64/kernel/process.c | 56 ++++++++++++++++++++++++++++++++++++++ arch/arm64/mm/Makefile | 1 + arch/arm64/mm/gcs.c | 39 ++++++++++++++++++++++++++ 5 files changed, 126 insertions(+) diff --git a/arch/arm64/include/asm/gcs.h b/arch/arm64/include/asm/gcs.h index 7c5e95218db6..04594ef59dad 100644 --- a/arch/arm64/include/asm/gcs.h +++ b/arch/arm64/include/asm/gcs.h @@ -48,4 +48,28 @@ static inline u64 gcsss2(void) return Xt; } +#ifdef CONFIG_ARM64_GCS + +static inline bool task_gcs_el0_enabled(struct task_struct *task) +{ + return current->thread.gcs_el0_mode & PR_SHADOW_STACK_ENABLE; +} + +void gcs_set_el0_mode(struct task_struct *task); +void gcs_free(struct task_struct *task); +void gcs_preserve_current_state(void); + +#else + +static inline bool task_gcs_el0_enabled(struct task_struct *task) +{ + return false; +} + +static inline void gcs_set_el0_mode(struct task_struct *task) { } +static inline void gcs_free(struct task_struct *task) { } +static inline void gcs_preserve_current_state(void) { } + +#endif + #endif diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index f77371232d8c..c55e3600604a 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -184,6 +184,12 @@ struct thread_struct { u64 sctlr_user; u64 svcr; u64 tpidr2_el0; +#ifdef CONFIG_ARM64_GCS + unsigned int gcs_el0_mode; + u64 gcspr_el0; + u64 gcs_base; + u64 gcs_size; +#endif }; static inline unsigned int thread_get_vl(struct thread_struct *thread, diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 4ae31b7af6c3..5f00cb0da9c3 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -48,6 +48,7 @@ #include #include #include +#include #include #include #include @@ -271,12 +272,32 @@ static void flush_tagged_addr_state(void) clear_thread_flag(TIF_TAGGED_ADDR); } +#ifdef CONFIG_ARM64_GCS + +static void flush_gcs(void) +{ + if (!system_supports_gcs()) + return; + + gcs_free(current); + current->thread.gcs_el0_mode = 0; + write_sysreg_s(0, SYS_GCSCRE0_EL1); + write_sysreg_s(0, SYS_GCSPR_EL0); +} + +#else + +static void flush_gcs(void) { } + +#endif + void flush_thread(void) { fpsimd_flush_thread(); tls_thread_flush(); flush_ptrace_hw_breakpoint(current); flush_tagged_addr_state(); + flush_gcs(); } void arch_release_task_struct(struct task_struct *tsk) @@ -471,6 +492,40 @@ static void entry_task_switch(struct task_struct *next) __this_cpu_write(__entry_task, next); } +#ifdef CONFIG_ARM64_GCS + +void gcs_preserve_current_state(void) +{ + if (task_gcs_el0_enabled(current)) + current->thread.gcspr_el0 = read_sysreg_s(SYS_GCSPR_EL0); +} + +static void gcs_thread_switch(struct task_struct *next) +{ + if (!system_supports_gcs()) + return; + + gcs_preserve_current_state(); + + gcs_set_el0_mode(next); + write_sysreg_s(next->thread.gcspr_el0, SYS_GCSPR_EL0); + + /* + * Ensure that GCS changes are observable by/from other PEs in + * case of migration. + */ + if (task_gcs_el0_enabled(current) || task_gcs_el0_enabled(next)) + gcsb_dsync(); +} + +#else + +static void gcs_thread_switch(struct task_struct *next) +{ +} + +#endif + /* * ARM erratum 1418040 handling, affecting the 32bit view of CNTVCT. * Ensure access is disabled when switching to a 32bit task, ensure @@ -530,6 +585,7 @@ struct task_struct *__switch_to(struct task_struct *prev, ssbs_thread_switch(next); erratum_1418040_thread_switch(next); ptrauth_thread_switch_user(next); + gcs_thread_switch(next); /* * Complete any pending TLB or cache maintenance on this CPU in case diff --git a/arch/arm64/mm/Makefile b/arch/arm64/mm/Makefile index 60454256945b..1a7b3a2f21e6 100644 --- a/arch/arm64/mm/Makefile +++ b/arch/arm64/mm/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_TRANS_TABLE) += trans_pgd.o obj-$(CONFIG_TRANS_TABLE) += trans_pgd-asm.o obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o obj-$(CONFIG_ARM64_MTE) += mteswap.o +obj-$(CONFIG_ARM64_GCS) += gcs.o KASAN_SANITIZE_physaddr.o += n obj-$(CONFIG_KASAN) += kasan_init.o diff --git a/arch/arm64/mm/gcs.c b/arch/arm64/mm/gcs.c new file mode 100644 index 000000000000..b0a67efc522b --- /dev/null +++ b/arch/arm64/mm/gcs.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include + +#include +#include + +/* + * Apply the GCS mode configured for the specified task to the + * hardware. + */ +void gcs_set_el0_mode(struct task_struct *task) +{ + u64 gcscre0_el1 = GCSCRE0_EL1_nTR; + + if (task->thread.gcs_el0_mode & PR_SHADOW_STACK_ENABLE) + gcscre0_el1 |= GCSCRE0_EL1_RVCHKEN | GCSCRE0_EL1_PCRSEL; + + if (task->thread.gcs_el0_mode & PR_SHADOW_STACK_WRITE) + gcscre0_el1 |= GCSCRE0_EL1_STREn; + + if (task->thread.gcs_el0_mode & PR_SHADOW_STACK_PUSH) + gcscre0_el1 |= GCSCRE0_EL1_PUSHMEn; + + write_sysreg_s(gcscre0_el1, SYS_GCSCRE0_EL1); +} + +void gcs_free(struct task_struct *task) +{ + if (task->thread.gcs_base) + vm_munmap(task->thread.gcs_base, task->thread.gcs_size); + + task->thread.gcspr_el0 = 0; + task->thread.gcs_base = 0; + task->thread.gcs_size = 0; +}