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Thu, 22 Aug 2024 08:12:50 -0700 (PDT) From: Joey Gouly To: linux-arm-kernel@lists.infradead.org Cc: nd@arm.com, akpm@linux-foundation.org, aneesh.kumar@kernel.org, aneesh.kumar@linux.ibm.com, anshuman.khandual@arm.com, bp@alien8.de, broonie@kernel.org, catalin.marinas@arm.com, christophe.leroy@csgroup.eu, dave.hansen@linux.intel.com, hpa@zytor.com, joey.gouly@arm.com, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linuxppc-dev@lists.ozlabs.org, maz@kernel.org, mingo@redhat.com, mpe@ellerman.id.au, naveen.n.rao@linux.ibm.com, npiggin@gmail.com, oliver.upton@linux.dev, shuah@kernel.org, skhan@linuxfoundation.org, szabolcs.nagy@arm.com, tglx@linutronix.de, will@kernel.org, x86@kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org Subject: [PATCH v5 21/30] arm64: enable POE and PIE to coexist Date: Thu, 22 Aug 2024 16:11:04 +0100 Message-Id: <20240822151113.1479789-22-joey.gouly@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240822151113.1479789-1-joey.gouly@arm.com> References: <20240822151113.1479789-1-joey.gouly@arm.com> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: 0A5EC140004 X-Stat-Signature: ciwnmfukwnpxu7qqccb7quq73wh1ncer X-HE-Tag: 1724339575-854841 X-HE-Meta: U2FsdGVkX1/oHE/WzS28YUht+HTMwH6fGHGrzvtBLwhh5vfz315q2ZyUU1kPjVg7yz2qjE8tSikGpqUzr3SqY8f4l63ClPbUaK8cseVUDWKm/NtvD9WUGFxwH2xvhlhLVEXR/i3exPgbp6JwtY5Rn0sBjM2gqQ51N6exGaMzJsDKblGp4QaDistcvz5KUzlUIgyKMOwRoP1rZ+A7OjUosclkBcGo04yuXDOogFogknt6v2nxjYSRfoyYKfegrNi19fb7mHys6JVJqzHxOOgOff/yDxVXKjyTsBmUNYTCQEXGYu9rG+AEW3d6kTmqn4AGF7UWOjvB+7RIvkhgNAnyVT5kgbJ6rmn9l7I++9+UBD/c9qE6ISVjX00mQvQfMnRlN6o+7q1LinkGWCT9N7ZSD1n7M6Uf4KZw4jrpBNe9qPmo0oCzEBzeO0WUt1ClX1Z/I+m9AplfCE885OzjKbi0bZvif0N3kujk3LStjNnmbu0MrU8AclfCMDNKTcDUVP67KK9hVRLncck+L52fir7uTJSkjDegT+BkUdolA61jjc3yE8PwMDmi2g6gcCexcZ3vSemGYcgTfNB5fcdEm8t8VFxqvbQqXfcG3LcJel/mQjSeigqAEB2KOUuN35d0xH+GDEYgk1KGRosqOOsNnFjjP9sdL6nG3rbz5eRN2ZWxDaCxKXHCBWaGDLNwXbH5QuLhr3m+31YJ143ljyhLLsGpN/XWvrzwnPzAe5xX+aPonrFsbHi0YxnmP4WENHrptrtMCscFXMavmjLs/NQJC6aQfZr2xmMHp2Yi3IP2FXcoz/PungUsy7NhYxtd6F6Lh2SHh3O9rAlaxPs56okhD2IPqcyFjY8tQXMyveuu2a5IaIFr6WktMjvl9/2sZwiL+wmrtgOzIQI96gNgU1l0XS8t5E50oYXSUpZDgRYkS2j/egD5cQLpsbYNgEl/KZpecRvugAl40XAB/DcUbdmjVkx 4X4GkLXe f+LaDjdY8Ct52FEHO/RWyTbBp4k+5p7MXe2oH/fMuHKFK/sO3p2cYRUlu4gJJgBcPp/G2ZpzE5t5rRnSyySi5v01+iYggdsASLos+epp76GLvGdFO8oqPb0DpISXe7PUaZ0ZWwCrI9zQJqzV5yFDYFs0j3wSUbejYjBCNH7w3595bYI74vvf5x4UEg/BHko2l18hJvYue0OXzwMCHXFe7d0+Jzw== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Permission Indirection Extension and Permission Overlay Extension can be enabled independently. When PIE is disabled and POE is enabled, the permissions set by POR_EL0 will be applied on top of the permissions set in the PTE. When both PIE and POE are enabled, the permissions set by POR_EL0 will be applied on top of the permissions set by the PIRE0_EL1 register. However PIRE0_EL1 has encodings that specifically enable and disable the overlay from applying. For example: 0001 Read, Overlay applied. 1000 Read, Overlay not applied. Switch to using the 'Overlay applied' encodings in PIRE0_EL1, so that PIE and POE can coexist. Signed-off-by: Joey Gouly Cc: Catalin Marinas Cc: Will Deacon Reviewed-by: Catalin Marinas --- arch/arm64/include/asm/pgtable-prot.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git arch/arm64/include/asm/pgtable-prot.h arch/arm64/include/asm/pgtable-prot.h index b11cfb9fdd37..2a11d0c10760 100644 --- arch/arm64/include/asm/pgtable-prot.h +++ arch/arm64/include/asm/pgtable-prot.h @@ -154,10 +154,10 @@ static inline bool __pure lpa2_is_enabled(void) #define PIE_E0 ( \ PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECONLY), PIE_X_O) | \ - PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY_EXEC), PIE_RX) | \ - PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED_EXEC), PIE_RWX) | \ - PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY), PIE_R) | \ - PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED), PIE_RW)) + PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY_EXEC), PIE_RX_O) | \ + PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED_EXEC), PIE_RWX_O) | \ + PIRx_ELx_PERM(pte_pi_index(_PAGE_READONLY), PIE_R_O) | \ + PIRx_ELx_PERM(pte_pi_index(_PAGE_SHARED), PIE_RW_O)) #define PIE_E1 ( \ PIRx_ELx_PERM(pte_pi_index(_PAGE_EXECONLY), PIE_NONE_O) | \