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AJvYcCUvTYWTT/ghOjyzYOAl5+I3Vvbp72n+8ytesb4c5qFBcKSemNeWW6vw4gNC+V9HtptewqVPYQqtuQ==@kvack.org X-Gm-Message-State: AOJu0YwQnyN63xCsCraiFEOvmPsD4nX81QVTrzYMOX2wplPIEpwVUI8F zChPfXFxEtIpAPNi0mzbnq9p9L4QXOpT5mfcFx1s/k47mSBkFdneiM9fafufPmo= X-Google-Smtp-Source: AGHT+IF7CFCu96gm/xkq1N6i1yXTt9iSzasTjNEzOjllTvd3QLn/Kdw4NOydn5m2u4mcpVddzMAc9Q== X-Received: by 2002:a17:90b:3808:b0:2cf:def1:d1eb with SMTP id 98e67ed59e1d1-2db9ff74692mr5469461a91.8.1726183135597; Thu, 12 Sep 2024 16:18:55 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2db6c1ac69asm3157591a91.0.2024.09.12.16.18.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Sep 2024 16:18:55 -0700 (PDT) From: Deepak Gupta To: paul.walmsley@sifive.com, palmer@sifive.com, conor@kernel.org, linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-kselftest@vger.kernel.org Cc: corbet@lwn.net, palmer@dabbelt.com, aou@eecs.berkeley.edu, robh@kernel.org, krzk+dt@kernel.org, oleg@redhat.com, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, peterz@infradead.org, akpm@linux-foundation.org, arnd@arndb.de, ebiederm@xmission.com, kees@kernel.org, Liam.Howlett@oracle.com, vbabka@suse.cz, lorenzo.stoakes@oracle.com, shuah@kernel.org, brauner@kernel.org, samuel.holland@sifive.com, debug@rivosinc.com, andy.chiu@sifive.com, jerry.shih@sifive.com, greentime.hu@sifive.com, charlie@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, xiao.w.wang@intel.com, ajones@ventanamicro.com, anup@brainfault.org, mchitale@ventanamicro.com, atishp@rivosinc.com, sameo@rivosinc.com, bjorn@rivosinc.com, alexghiti@rivosinc.com, david@redhat.com, libang.li@antgroup.com, jszhang@kernel.org, leobras@redhat.com, guoren@kernel.org, samitolvanen@google.com, songshuaishuai@tinylab.org, costa.shul@redhat.com, bhe@redhat.com, zong.li@sifive.com, puranjay@kernel.org, namcaov@gmail.com, antonb@tenstorrent.com, sorear@fastmail.com, quic_bjorande@quicinc.com, ancientmodern4@gmail.com, ben.dooks@codethink.co.uk, quic_zhonhan@quicinc.com, cuiyunhui@bytedance.com, yang.lee@linux.alibaba.com, ke.zhao@shingroup.cn, sunilvl@ventanamicro.com, tanzhasanwork@gmail.com, schwab@suse.de, dawei.li@shingroup.cn, rppt@kernel.org, willy@infradead.org, usama.anjum@collabora.com, osalvador@suse.de, ryan.roberts@arm.com, andrii@kernel.org, alx@kernel.org, catalin.marinas@arm.com, broonie@kernel.org, revest@chromium.org, bgray@linux.ibm.com, deller@gmx.de, zev@bewilderbeest.net Subject: [PATCH v4 25/30] riscv/ptrace: riscv cfi status and state via ptrace and in core files Date: Thu, 12 Sep 2024 16:16:44 -0700 Message-ID: <20240912231650.3740732-26-debug@rivosinc.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20240912231650.3740732-1-debug@rivosinc.com> References: <20240912231650.3740732-1-debug@rivosinc.com> MIME-Version: 1.0 X-Stat-Signature: qhnkepxyreqyx7ji4gfiafpttux7jyng X-Rspamd-Queue-Id: DE12780014 X-Rspam-User: X-Rspamd-Server: rspam08 X-HE-Tag: 1726183136-666024 X-HE-Meta: U2FsdGVkX19P/DgewVmREb5nJNYBH+Xlqh7cuv2oYKWpIdFMoeRG8rSNic2U05zYFk4uv12CNI4xzCw5nR33CH1o6smfljJ8tF8pSvo3jpWdMPxrg3u4rv5r3Q6NmMr8H5Mm5AA7dap9oLNSUwk1NgS/lVTFgbnU9GzkTyACR6mw6bRttFghs0GbPZebTcrxea1WA4yYi0D2GYilQHc93LUSDV+muwl/fofXXqATkqZ8UiGoQQkDfUw7KW52pqyPpBaNX5AMGQl4KgxMcnDOBeaycK7GZPlvq3AIRjqo+dgiTIFYelkWn/JUPNYFKo+HNGXVDh/ltrWwVHUr6t7UboQBmhhISCqlxN8268gr86o+w2gLmlIeh2LTbP/kSTn7GV0xoqfPxANBYBw7dw1aoTopJJyDumR8hoh3G9wZ3amE5FY+7AI8R2ktOFjZbyZdNFI4pR9a5Rofg37Vv5IyO6Xj4KEMdpSGCjTjs+xJnR3sz8/q+7kcRAv0QDNeZ+uNuCG9BipNZ+5nD+sJs4AXHo0Iu/FxQL9vPH1NHTQlbj78m7dwUdUPATPbusTR42Kw1ku4sWXBj1oSxzu1s/vnrDxbCnyq220eMooJ3aYjFQWB1gsfPktly12iILr8EKbkTHeVLNMbx62R3PS6Bry3Clm5biQHYv67PknJ0rQ6Zkbsr0fGcG888rnGYW45+JsbzNVPgjZQMAkYE3/RkcLZ7OG6iik29bbjk+8y3wSX3xx3tqlwNLwOzXrvLzrrAvz1HPoI8R47C+x2Uh2y7nego1kVW5THViS3fhU9vCdm8Nq3lD1ng51sjc3poEMJ6U3M0rlLixeb2GIoPOYx+arGQf1NG7z5wAFS9uGyfBZT1VsZWV+Xmrl9AU5vW5C6robfXHZLwxrLWSnlxa1UPMNBohoBbeWBMmMBQZqV79OZrTtUTZTJY8pEzWYxKwn527uoDGuqeTCDlVC8zjqAmEB DW8ZQfUb otNFVAiZUiYsY33+ZdLcJRF+g9KG97d2RlycJG2oAnDSsUWFSZWTL60xTtwaCNaUgNQfRkawuRwvS/mKg21qWVAtBMnv1HJ2Gi7bB3pJFp+XcPinS1vRCLGCroUcQoxxi+32g0CsNSi/V60HIo2pxwc7v1pGskGFczdupTiMuA3gAjQQdivDqWFfT0NuK+lYR4tJEhq7xnE1a+thbL47OfhNsLQzsQhSIiIrsBzNg18Z7NQcvtanc1Q65gh5ZjyBKOffYvMHQ9lXrQNWA72WmemY0fd6Br/YOUlu0vg30tlRSzU/ljhXoDBHW0Jzf+h6wDReUDrYWEnsnYSbJTCd6SABiDC1gW8I5gGkVTqq7uQ1Ku91vTT6WH9ti0QQOGSv+LByr/hqWLHzKxw3/2oslK7n3+VCLHZXMOFTNpSqWxV2zt3U= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Expose a new register type NT_RISCV_USER_CFI for risc-v cfi status and state. Intentionally both landing pad and shadow stack status and state are rolled into cfi state. Creating two different NT_RISCV_USER_XXX would not be useful and wastage of a note type. Enabling or disabling of feature is not allowed via ptrace set interface. However setting `elp` state or setting shadow stack pointer are allowed via ptrace set interface. It is expected `gdb` might have use to fixup `elp` state or `shadow stack` pointer. Signed-off-by: Deepak Gupta --- arch/riscv/include/uapi/asm/ptrace.h | 18 ++++++ arch/riscv/kernel/ptrace.c | 83 ++++++++++++++++++++++++++++ include/uapi/linux/elf.h | 1 + 3 files changed, 102 insertions(+) diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi/asm/ptrace.h index a38268b19c3d..512be06a8661 100644 --- a/arch/riscv/include/uapi/asm/ptrace.h +++ b/arch/riscv/include/uapi/asm/ptrace.h @@ -127,6 +127,24 @@ struct __riscv_v_regset_state { */ #define RISCV_MAX_VLENB (8192) +struct __cfi_status { + /* indirect branch tracking state */ + __u64 lp_en : 1; + __u64 lp_lock : 1; + __u64 elp_state : 1; + + /* shadow stack status */ + __u64 shstk_en : 1; + __u64 shstk_lock : 1; + + __u64 rsvd : sizeof(__u64) - 5; +}; + +struct user_cfi_state { + struct __cfi_status cfi_status; + __u64 shstk_ptr; +}; + #endif /* __ASSEMBLY__ */ #endif /* _UAPI_ASM_RISCV_PTRACE_H */ diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c index 92731ff8c79a..c69b20ea6e79 100644 --- a/arch/riscv/kernel/ptrace.c +++ b/arch/riscv/kernel/ptrace.c @@ -19,6 +19,7 @@ #include #include #include +#include enum riscv_regset { REGSET_X, @@ -28,6 +29,9 @@ enum riscv_regset { #ifdef CONFIG_RISCV_ISA_V REGSET_V, #endif +#ifdef CONFIG_RISCV_USER_CFI + REGSET_CFI, +#endif }; static int riscv_gpr_get(struct task_struct *target, @@ -152,6 +156,75 @@ static int riscv_vr_set(struct task_struct *target, } #endif +#ifdef CONFIG_RISCV_USER_CFI +static int riscv_cfi_get(struct task_struct *target, + const struct user_regset *regset, + struct membuf to) +{ + struct user_cfi_state user_cfi; + struct pt_regs *regs; + + regs = task_pt_regs(target); + + user_cfi.cfi_status.lp_en = is_indir_lp_enabled(target); + user_cfi.cfi_status.lp_lock = is_indir_lp_locked(target); + user_cfi.cfi_status.elp_state = (regs->status & SR_ELP); + + user_cfi.cfi_status.shstk_en = is_shstk_enabled(target); + user_cfi.cfi_status.shstk_lock = is_shstk_locked(target); + user_cfi.shstk_ptr = get_active_shstk(target); + + return membuf_write(&to, &user_cfi, sizeof(user_cfi)); +} + +/* + * Does it make sense to allowing enable / disable of cfi via ptrace? + * Not allowing enable / disable / locking control via ptrace for now. + * Setting shadow stack pointer is allowed. GDB might use it to unwind or + * some other fixup. Similarly gdb might want to suppress elp and may want + * to reset elp state. + */ +static int riscv_cfi_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int ret; + struct user_cfi_state user_cfi; + struct pt_regs *regs; + + regs = task_pt_regs(target); + + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &user_cfi, 0, -1); + if (ret) + return ret; + + /* + * Not allowing enabling or locking shadow stack or landing pad + * There is no disabling of shadow stack or landing pad via ptrace + * rsvd field should be set to zero so that if those fields are needed in future + */ + if (user_cfi.cfi_status.lp_en || user_cfi.cfi_status.lp_lock || + user_cfi.cfi_status.shstk_en || user_cfi.cfi_status.shstk_lock || + !user_cfi.cfi_status.rsvd) + return -EINVAL; + + /* If lpad is enabled on target and ptrace requests to set / clear elp, do that */ + if (is_indir_lp_enabled(target)) { + if (user_cfi.cfi_status.elp_state) /* set elp state */ + regs->status |= SR_ELP; + else + regs->status &= ~SR_ELP; /* clear elp state */ + } + + /* If shadow stack enabled on target, set new shadow stack pointer */ + if (is_shstk_enabled(target)) + set_active_shstk(target, user_cfi.shstk_ptr); + + return 0; +} +#endif + static const struct user_regset riscv_user_regset[] = { [REGSET_X] = { .core_note_type = NT_PRSTATUS, @@ -182,6 +255,16 @@ static const struct user_regset riscv_user_regset[] = { .set = riscv_vr_set, }, #endif +#ifdef CONFIG_RISCV_USER_CFI + [REGSET_CFI] = { + .core_note_type = NT_RISCV_USER_CFI, + .align = sizeof(__u64), + .n = sizeof(struct user_cfi_state) / sizeof(__u64), + .size = sizeof(__u64), + .regset_get = riscv_cfi_get, + .set = riscv_cfi_set, + } +#endif }; static const struct user_regset_view riscv_user_native_view = { diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index b54b313bcf07..390732883fd7 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -448,6 +448,7 @@ typedef struct elf64_shdr { #define NT_MIPS_MSA 0x802 /* MIPS SIMD registers */ #define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */ #define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */ +#define NT_RISCV_USER_CFI 0x902 /* RISC-V shadow stack state */ #define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */ #define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */ #define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension registers */