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Tue, 01 Oct 2024 09:08:06 -0700 (PDT) From: Deepak Gupta Date: Tue, 01 Oct 2024 09:06:30 -0700 Subject: [PATCH 25/33] riscv/ptrace: riscv cfi status and state via ptrace and in core files MIME-Version: 1.0 Message-Id: <20241001-v5_user_cfi_series-v1-25-3ba65b6e550f@rivosinc.com> References: <20241001-v5_user_cfi_series-v1-0-3ba65b6e550f@rivosinc.com> In-Reply-To: <20241001-v5_user_cfi_series-v1-0-3ba65b6e550f@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta X-Mailer: b4 0.14.0 X-Rspam-User: X-Stat-Signature: 75z3i6y9appcrs13stcntyr1rdt8jnug X-Rspamd-Queue-Id: 42AD11C0016 X-Rspamd-Server: rspam02 X-HE-Tag: 1727798888-822894 X-HE-Meta: U2FsdGVkX1/Itu/HIiioBE+dNiizYBXaMdOTVpn+DB4UXtVjyMoi1S3U9bS7QWDxMzeY8FIT+S3k1RciwUSOVwswaONkxtpcMnaD6G0f/TmNapH2KpA01eTJZCWQkMKiKQJLA0fZmvRZ3L6s2GvqxZqugKdptYRPcGEW8+j7fXD7mc+8Q+ffUkouNzNoEBePdnDMbRlbHGOKxPa7oW2c1JLAdxmY/ImTe4nKIM4UIkZXAnQUCGykgglUgj0Aa4LjaOBD3R0It66v37XDFB4niBT78dpxct7ze5IHSzlQvFUUAS2OJDRhdcMs2mQWpWXMFfRhKOhhlwRnkByQMH3yG26EjMRoZU3FepXbBL996ApTX6VerSdxhUxepaS8m6RlLLt/y9BKRlHM/ghRcp54G6/SzNZJdQdobBONC3uXGsMsbf0kFxscSuHDxv8WLLP/jFuZCpyYkOCPJd6NKtki1c6xVxtRiOLav0RDAx5wbJy7Fr75Hf0L+4Vav+SBIrZnR1v3hCWJjG5/MCbwPGn2Vy5MRdgKdBlMA+u/VLQY1jKutTxTzE4AgvaSXzOkdjCPi7cYnI3FeoB/1u19I3Y6w87PxV5WAg4EMuxGs7g4JVs1A5HZHBuVPEcjB1ziJ+AjIJRZnVkBF3nwSxPkyo51BiqZk0tT1M38DnedkLJY4BsAR/VHJQVdRlDp+QMZ6E8JkGmKA8jtKjxoD1ifCw3tc7qJd0/7dCRtjwLvo9a6HILZUcwYqkEfa7s/7+GMKjEnfRsdDAMWBb8FsY8Rjtn2Uk68MSeMByyh4Q3gkCvuPIDWfPovfl1s3wPTfYIy9ZtY1uSSKhaR4aZjv34L345D9+5Tr3rIDUl1BdwuqdRhO6M6N3inwj0yjDMQNm9Yy6wAdEW4zQ5gSaGT44xYdQI59LLuGOuE99QKblY6XWsotAqIU54mHvuypKqprIdNqoUPCIO1I4S6YtjpAkrSqU4 AZtEzqnT hey2D1DSGbJlgT3JKjHf7NJ3zkLP7zifuniOGUuNPB485JnALIHvaUbDdIzgWNKJmRAt6MSs9x5dUK+LE63bbk9KkLHsoaFMfL06hDIXVor1DA1DRplgm9ke8QDT4srHkd0+tHqocxI7BGL/UCqFmGGhhARh8ug/pMGVKSCEyDTZRfrfwuqufot+UzjdjPt7gl+SZoUa9BipQaAr5Sw5HuqWqWeCWvQVc39faBLPx30We6hpxa5EK5UtAUI/vsWQxwEkP7gD0YMKX/bK06mcQ5PeT8v6bBVMfyTXmngU7WlaeXYW1GSyVl18boskZOwK2G9Q5Pp1IOuVLJq1GdZz91N6cwSrYCHtnIAitJUl4ASzEwjGmlX8Hir+Ysw1PKgBz0WS3wOfSjkuaK8iBugi5Nwi7aMxSuYpJXrVxRmrEjunEN0HPo5QONRgu+LjMG3GddWf6M6QMRS1+oj0= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Expose a new register type NT_RISCV_USER_CFI for risc-v cfi status and state. Intentionally both landing pad and shadow stack status and state are rolled into cfi state. Creating two different NT_RISCV_USER_XXX would not be useful and wastage of a note type. Enabling or disabling of feature is not allowed via ptrace set interface. However setting `elp` state or setting shadow stack pointer are allowed via ptrace set interface. It is expected `gdb` might have use to fixup `elp` state or `shadow stack` pointer. Signed-off-by: Deepak Gupta --- arch/riscv/include/uapi/asm/ptrace.h | 18 ++++++++ arch/riscv/kernel/ptrace.c | 83 ++++++++++++++++++++++++++++++++++++ include/uapi/linux/elf.h | 1 + 3 files changed, 102 insertions(+) diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi/asm/ptrace.h index 659ea3af5680..e6571fba8a8a 100644 --- a/arch/riscv/include/uapi/asm/ptrace.h +++ b/arch/riscv/include/uapi/asm/ptrace.h @@ -131,6 +131,24 @@ struct __sc_riscv_cfi_state { unsigned long ss_ptr; /* shadow stack pointer */ }; +struct __cfi_status { + /* indirect branch tracking state */ + __u64 lp_en : 1; + __u64 lp_lock : 1; + __u64 elp_state : 1; + + /* shadow stack status */ + __u64 shstk_en : 1; + __u64 shstk_lock : 1; + + __u64 rsvd : sizeof(__u64) - 5; +}; + +struct user_cfi_state { + struct __cfi_status cfi_status; + __u64 shstk_ptr; +}; + #endif /* __ASSEMBLY__ */ #endif /* _UAPI_ASM_RISCV_PTRACE_H */ diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c index 92731ff8c79a..c69b20ea6e79 100644 --- a/arch/riscv/kernel/ptrace.c +++ b/arch/riscv/kernel/ptrace.c @@ -19,6 +19,7 @@ #include #include #include +#include enum riscv_regset { REGSET_X, @@ -28,6 +29,9 @@ enum riscv_regset { #ifdef CONFIG_RISCV_ISA_V REGSET_V, #endif +#ifdef CONFIG_RISCV_USER_CFI + REGSET_CFI, +#endif }; static int riscv_gpr_get(struct task_struct *target, @@ -152,6 +156,75 @@ static int riscv_vr_set(struct task_struct *target, } #endif +#ifdef CONFIG_RISCV_USER_CFI +static int riscv_cfi_get(struct task_struct *target, + const struct user_regset *regset, + struct membuf to) +{ + struct user_cfi_state user_cfi; + struct pt_regs *regs; + + regs = task_pt_regs(target); + + user_cfi.cfi_status.lp_en = is_indir_lp_enabled(target); + user_cfi.cfi_status.lp_lock = is_indir_lp_locked(target); + user_cfi.cfi_status.elp_state = (regs->status & SR_ELP); + + user_cfi.cfi_status.shstk_en = is_shstk_enabled(target); + user_cfi.cfi_status.shstk_lock = is_shstk_locked(target); + user_cfi.shstk_ptr = get_active_shstk(target); + + return membuf_write(&to, &user_cfi, sizeof(user_cfi)); +} + +/* + * Does it make sense to allowing enable / disable of cfi via ptrace? + * Not allowing enable / disable / locking control via ptrace for now. + * Setting shadow stack pointer is allowed. GDB might use it to unwind or + * some other fixup. Similarly gdb might want to suppress elp and may want + * to reset elp state. + */ +static int riscv_cfi_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int ret; + struct user_cfi_state user_cfi; + struct pt_regs *regs; + + regs = task_pt_regs(target); + + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &user_cfi, 0, -1); + if (ret) + return ret; + + /* + * Not allowing enabling or locking shadow stack or landing pad + * There is no disabling of shadow stack or landing pad via ptrace + * rsvd field should be set to zero so that if those fields are needed in future + */ + if (user_cfi.cfi_status.lp_en || user_cfi.cfi_status.lp_lock || + user_cfi.cfi_status.shstk_en || user_cfi.cfi_status.shstk_lock || + !user_cfi.cfi_status.rsvd) + return -EINVAL; + + /* If lpad is enabled on target and ptrace requests to set / clear elp, do that */ + if (is_indir_lp_enabled(target)) { + if (user_cfi.cfi_status.elp_state) /* set elp state */ + regs->status |= SR_ELP; + else + regs->status &= ~SR_ELP; /* clear elp state */ + } + + /* If shadow stack enabled on target, set new shadow stack pointer */ + if (is_shstk_enabled(target)) + set_active_shstk(target, user_cfi.shstk_ptr); + + return 0; +} +#endif + static const struct user_regset riscv_user_regset[] = { [REGSET_X] = { .core_note_type = NT_PRSTATUS, @@ -182,6 +255,16 @@ static const struct user_regset riscv_user_regset[] = { .set = riscv_vr_set, }, #endif +#ifdef CONFIG_RISCV_USER_CFI + [REGSET_CFI] = { + .core_note_type = NT_RISCV_USER_CFI, + .align = sizeof(__u64), + .n = sizeof(struct user_cfi_state) / sizeof(__u64), + .size = sizeof(__u64), + .regset_get = riscv_cfi_get, + .set = riscv_cfi_set, + } +#endif }; static const struct user_regset_view riscv_user_native_view = { diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index b9935988da5c..7ef63b2b67a1 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -450,6 +450,7 @@ typedef struct elf64_shdr { #define NT_MIPS_MSA 0x802 /* MIPS SIMD registers */ #define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */ #define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */ +#define NT_RISCV_USER_CFI 0x902 /* RISC-V shadow stack state */ #define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */ #define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */ #define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension registers */