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Tue, 01 Oct 2024 09:07:09 -0700 (PDT) From: Deepak Gupta Date: Tue, 01 Oct 2024 09:06:09 -0700 Subject: [PATCH 04/33] riscv: Add support for per-thread envcfg CSR values MIME-Version: 1.0 Message-Id: <20241001-v5_user_cfi_series-v1-4-3ba65b6e550f@rivosinc.com> References: <20241001-v5_user_cfi_series-v1-0-3ba65b6e550f@rivosinc.com> In-Reply-To: <20241001-v5_user_cfi_series-v1-0-3ba65b6e550f@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta , Samuel Holland , Andrew Jones X-Mailer: b4 0.14.0 X-Rspamd-Server: rspam12 X-Rspamd-Queue-Id: 08899120035 X-Stat-Signature: qdc7bfgaben7u4eskspqfj8pkfw45yzy X-Rspam-User: X-HE-Tag: 1727798830-328273 X-HE-Meta: U2FsdGVkX1/ke17L3M5fyHFlAHt97YX1qxdPIvMz4dftflER8oPLU1chPibNvtdYrO6WfW8yYXjcQlerb9ic8jBmqo9JtQIgzooFiFA0VIPz0Ne1iW6U/JYeuSAK+zLeeyjJtZkKdDcgm0fNQcYxiim+OiJXm5rdy3/Y7B8g3t7BqcEwzh6TtLbWk/j1F9HsCj5yrwmztUXXz9EcaFLMLpKwijNSfoLOrJ9LatcVQX27pXpOTEQeW7ZIMXzGm9kQcUplqU71nKpjgI4uKQf1Ib5993whHTxeG7SL6W2Qwiu/2SUdix7Ma5vIqYhMl5DjXGBvouck8SUseNyqIl1rGc74t67a5O7i+9MXmDnw7yMH1HxVIHiOUQI6WjUriiiT5j6Htgx1yfTBv2sCPI5pUD8tzs+tHkBmaaRz2xC3lImx4eypK9DvKDBGi1HHeMg3W8TaxhzkzXrMAQravGlzSYMu4d6WkNwBUeBcvnQC3TsW5AfoPwDOgRjpNeGpsfMq4V/rQFSJ9WBdkw5FAldUTVHE75C3PBTVslUQYRw0WPCOVhETayVphaL3Wj8fEC/+JGpirhCc9QFK9aF1dDeaVTV3sMRuCL0VHcIFcxhLzjErHEVc6nVbldE33AvNHdu7G04EKBICy2ppecunA9fLq9XPZegiEC7QOfhbOOGDId8sM0zoOLBFiX41GitfoX1nma08cVClE0jHA9pQ45Dl9GOeCKpBOfdJzvjRkQtSbe3yjJGuXagv/Y+kBYpu618y12qBfzMgGopRWVwoRjW3S3WpZXOA+nb8J7BI9ZVFkT5VAmgciFa9FFrK1cZHMMbJ1kq1v2/+sRm26oO3x5cVJIzx4Ns2ikYVd6lOs88ci2PgeQLL7wCcECuaBgxdftffaG9HeCeWOtM+hwat3B/m2sf2TcsZpycbzSgitqMv13Pk+GMpQm5zunb9/HepTJc3BSUsis++KijVqPV6RQw HTpDxPgm RAj/VDFoXGIsxJqoNdksjMAZ+C4WExIqzUCzWC7dG5cSLGd8o+Wt7CzVJeqLAgg19WnrzdSDMvR6//3zR5AOwaEjsebeeCk0KQnayjrM+x+A0n+P0iMdaMedxEjyC8P9iCUPXXvGj9EHAQ3rHsUTPtDVmj1V2hUH+a97s+7GgRa49To8Nx+SOPLGY3K1+94dUK4T4INEbzbfy7+W9tk1pbuOS9voJifxyssrGWpS+OigOPq9jsrDgqVbc9ShH5ouulguK2vAZcBxs2FuKLklv0dh2dyZhgz+pUKPFK6GKk/ZACURy65YBiWb1/EhzgMrYXpwY1pjKl68KT5WjWVx5ly3KoS+7IGx/JggcK+dzY6PYkbAd4n6wofcHTtA9SXU19XIolyb00Vs/riD7i2mLq4Yt9TU8hYkw6Y7ImJX+jPdlo64kHzSCDkbhFJwCM45uwW9+03bZ3PwwRRUmLmlpugv9gco3SyuGL0zmSKkfv4y+R6h6cejshg6qWT3CVu6dWiSESW47OneWH+I5jG2WiWTW0ZcMwYUi5d8Vjf/6jVErtSnhJwOYBn0jzaUiOUr0vuZCVDAruxWcUfE= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: From: Samuel Holland Some bits in the [ms]envcfg CSR, such as the CFI state and pointer masking mode, need to be controlled on a per-thread basis. Support this by keeping a copy of the CSR value in struct thread_struct and writing it during context switches. It is safe to discard the old CSR value during the context switch because the CSR is modified only by software, so the CSR will remain in sync with the copy in thread_struct. Use ALTERNATIVE directly instead of riscv_has_extension_unlikely() to minimize branchiness in the context switching code. Since thread_struct is copied during fork(), setting the value for the init task sets the default value for all other threads. Reviewed-by: Andrew Jones Reviewed-by: Deepak Gupta Signed-off-by: Samuel Holland --- arch/riscv/include/asm/switch_to.h | 8 ++++++++ arch/riscv/include/asm/thread_info.h | 1 + arch/riscv/kernel/cpufeature.c | 2 +- 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index 7594df37cc9f..dd4a36ff4356 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -70,6 +70,13 @@ static __always_inline bool has_fpu(void) { return false; } #define __switch_to_fpu(__prev, __next) do { } while (0) #endif +static inline void __switch_to_envcfg(struct task_struct *next) +{ + asm volatile (ALTERNATIVE("nop", "csrw " __stringify(CSR_ENVCFG) ", %0", + 0, RISCV_ISA_EXT_XLINUXENVCFG, 1) + :: "r" (next->thread_info.envcfg) : "memory"); +} + extern struct task_struct *__switch_to(struct task_struct *, struct task_struct *); @@ -103,6 +110,7 @@ do { \ __switch_to_vector(__prev, __next); \ if (switch_to_should_flush_icache(__next)) \ local_flush_icache_all(); \ + __switch_to_envcfg(__next); \ ((last) = __switch_to(__prev, __next)); \ } while (0) diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/thread_info.h index ebe52f96da34..e494871071da 100644 --- a/arch/riscv/include/asm/thread_info.h +++ b/arch/riscv/include/asm/thread_info.h @@ -57,6 +57,7 @@ struct thread_info { long user_sp; /* User stack pointer */ int cpu; unsigned long syscall_work; /* SYSCALL_WORK_ flags */ + unsigned long envcfg; #ifdef CONFIG_SHADOW_CALL_STACK void *scs_base; void *scs_sp; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index e560a253e99b..c0986291696a 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -923,7 +923,7 @@ unsigned long riscv_get_elf_hwcap(void) void riscv_user_isa_enable(void) { if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOZ)) - csr_set(CSR_ENVCFG, ENVCFG_CBZE); + current->thread_info.envcfg |= ENVCFG_CBZE; else if (any_cpu_has_zicboz) pr_warn_once("Zicboz disabled as it is unavailable on some harts\n"); }