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Tue, 08 Oct 2024 15:39:11 -0700 (PDT) From: Deepak Gupta Date: Tue, 08 Oct 2024 15:37:12 -0700 Subject: [PATCH v6 30/33] riscv: create a config for shadow stack and landing pad instr support MIME-Version: 1.0 Message-Id: <20241008-v5_user_cfi_series-v6-30-60d9fe073f37@rivosinc.com> References: <20241008-v5_user_cfi_series-v6-0-60d9fe073f37@rivosinc.com> In-Reply-To: <20241008-v5_user_cfi_series-v6-0-60d9fe073f37@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta X-Mailer: b4 0.14.0 X-Rspam-User: X-Rspamd-Queue-Id: A771CC000B X-Rspamd-Server: rspam01 X-Stat-Signature: zknfg1tnqajtbxhxigntqptqhkfbz5iq X-HE-Tag: 1728427152-536379 X-HE-Meta: U2FsdGVkX18bfVGKPauqqDMJ0tQMgl/VGriP1q2WIpi2g/nBSpNjNLHNCKr1Pd1YwHvztqZ7HtsQNseTe8jP4DPdjm9wXih6pctSkMf5AynSEeVaJgq6iOzwD1Kteam5lOisAgfiB31kJLKl1Z92rxXTm5FcNUTJpzTGSe5IiwZBNTgdaqkAirCvcdXkpyDGk4c8ad+QoT/vFsUefYyIO89+pzRYesiYLl4AKrFZoNbnTi1/vSQjoUMwQHZAc2m7yRc3M0ZxtcGH881LD7bGcnV1lW3gVJetgM56iMuOBz1HfBAwb53XGOJwStJpN3rGd3f2hKC1lE9Tgc24fB0O9Y8xV1BGVJdn4ESbjJ4ewZoNWh8e0i1thbwn/jJLlCeL9q73HmfvLA6CaCoXFUvImqR2ajDwMbyybEvxjNEt46uyGjO1mz2mxDyziB3RDGhZHvMDHH0KBUabUekmnNl5jHOJEodcLMvYfoG+7ArWi9RmQLJn+P+NtTzmXRI0MY17y3V9doMyxmY/SP0i6g+1MGru7QvX6VMtzF0b2TCAnNThAfCbcQpxK37QT4IFT62l/sfaPU9fG8HdB08Lpc+kUNlB/ylpkB8JEzP9iMGaOgTgXWMvES2czxAVeHyn9fxInVIzTbnVA8lBwUL1Wr5/ZzXNcPQYXHx9XZ1WYAPTcLEN0oaPCGcJe8tkDuB9JWQdcb56EWb59U438srasMA9ev4c6vqCOJO1cIzlMaAXr/ZSuZbvdFyZqoNKp6BuvyHzjFAKJPimqhN811IhiF4oRd5ToH0bNK6khNcDig06WuUqHDvM686eZ57aWPZmWIW6z1wO2xMBhK0rpKYzjLC48/47TqQopJrRdxj9JUhNOoQQSmb2Fkiszbp+IcEfYbTJfKSr0t990n1c2nGx6gt3p7rcUcF5gKiO+wUTWqQqRihkUojBZfi8c6RDA7nsfchyd7dhMi6oscPPsSuTMej NFSqAE/D 3OKMyN3736S8W9XeicXg92lwQ9uVI0SlIGqNbiDSFQSF1qmJqmHyrpWoIhlyPzjyzamVUOChEM1dPxJ7RQuSTYByIX2KXRbnp4xeUEpelro/YWPEHDTwLfsfLT+TimtOdA38om/jv0sgGX2xbKYDLVtc4U/hRn2w0h50rXZRqe+OZKx4ZLSEMsCj3ZLT65d1GhVr3TAgeuea1xz3Ldtxf/8uvcng0U2PDZrMvcWnW95/HT4VPfNE/RqOqcsStAg1aP6sAdcZWigLkcoPER1rwI6wHl0VeUtCWuHAYk3qy5KSkGTaKf9M9felXE6vIqCtSFB/OKDmKe1RcuGKWtJNCpwhiJh1Wvuo9OJOtZDAJy6wn4pEui+pCpuufMmKkfQT4wBVHGsa/xzbCn6cxxTokUm8f5e2Csi5sh/FiwQRYFHqeX9HP90XVcPon7cSSZ1kdQtY8Mauf5yG29cGQfu5DeqI3Km7D7r6l6Joe4GSgFerjpU8= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: This patch creates a config for shadow stack support and landing pad instr support. Shadow stack support and landing instr support can be enabled by selecting `CONFIG_RISCV_USER_CFI`. Selecting `CONFIG_RISCV_USER_CFI` wires up path to enumerate CPU support and if cpu support exists, kernel will support cpu assisted user mode cfi. If CONFIG_RISCV_USER_CFI is selected, select `ARCH_USES_HIGH_VMA_FLAGS`, `ARCH_HAS_USER_SHADOW_STACK` and DYNAMIC_SIGFRAME for riscv. Signed-off-by: Deepak Gupta --- arch/riscv/Kconfig | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 808ea66b9537..1335dbe91ab9 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -245,6 +245,26 @@ config ARCH_HAS_BROKEN_DWARF5 # https://github.com/llvm/llvm-project/commit/7ffabb61a5569444b5ac9322e22e5471cc5e4a77 depends on LD_IS_LLD && LLD_VERSION < 180000 +config RISCV_USER_CFI + def_bool y + bool "riscv userspace control flow integrity" + depends on 64BIT && $(cc-option,-mabi=lp64 -march=rv64ima_zicfiss) + depends on RISCV_ALTERNATIVE + select ARCH_HAS_USER_SHADOW_STACK + select ARCH_USES_HIGH_VMA_FLAGS + select DYNAMIC_SIGFRAME + help + Provides CPU assisted control flow integrity to userspace tasks. + Control flow integrity is provided by implementing shadow stack for + backward edge and indirect branch tracking for forward edge in program. + Shadow stack protection is a hardware feature that detects function + return address corruption. This helps mitigate ROP attacks. + Indirect branch tracking enforces that all indirect branches must land + on a landing pad instruction else CPU will fault. This mitigates against + JOP / COP attacks. Applications must be enabled to use it, and old user- + space does not get protection "for free". + default y + config ARCH_MMAP_RND_BITS_MIN default 18 if 64BIT default 8