| Message ID | 20241009124120.1124-17-shiju.jose@huawei.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | EDAC: Scrub: introduce generic EDAC RAS control feature driver + CXL/ACPI-RAS2 drivers | expand |
On Wed, 9 Oct 2024 13:41:17 +0100 <shiju.jose@huawei.com> wrote: > From: Shiju Jose <shiju.jose@huawei.com> > > Add support for PERFORM_MAINTENANCE mailbox command. > > CXL spec 3.1 section 8.2.9.7.1 describes the Perform Maintenance command. > This command requests the device to execute the maintenance operation > specified by the maintenance operation class and the maintenance operation > subclass. > > Signed-off-by: Shiju Jose <shiju.jose@huawei.com> One trivial comment. With that tidied up Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > drivers/cxl/core/mbox.c | 40 ++++++++++++++++++++++++++++++++++++++++ > drivers/cxl/cxlmem.h | 17 +++++++++++++++++ > 2 files changed, 57 insertions(+) > > diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c > index 30c44ab11347..a6f69864c504 100644 > --- a/drivers/cxl/core/mbox.c > +++ b/drivers/cxl/core/mbox.c > @@ -1084,6 +1084,46 @@ int cxl_set_feature(struct cxl_memdev_state *mds, > } > EXPORT_SYMBOL_NS_GPL(cxl_set_feature, CXL); > > +int cxl_do_maintenance(struct cxl_memdev_state *mds, > + u8 class, u8 subclass, > + void *data_in, size_t data_in_size) > +{ > + struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox; > + struct cxl_memdev_maintenance_pi { > + struct cxl_mbox_do_maintenance_hdr hdr; > + u8 data[]; > + } __packed; > + struct cxl_mbox_cmd mbox_cmd; > + size_t hdr_size; > + int rc = 0; Always set, so no need to init. > + > + struct cxl_memdev_maintenance_pi *pi __free(kfree) = > + kmalloc(cxl_mbox->payload_size, GFP_KERNEL); > + pi->hdr.op_class = class; > + pi->hdr.op_subclass = subclass; > + hdr_size = sizeof(pi->hdr); > + /* > + * Check minimum mbox payload size is available for > + * the maintenance data transfer. > + */ > + if (hdr_size + data_in_size > cxl_mbox->payload_size) > + return -ENOMEM; > + > + memcpy(pi->data, data_in, data_in_size); > + mbox_cmd = (struct cxl_mbox_cmd) { > + .opcode = CXL_MBOX_OP_DO_MAINTENANCE, > + .size_in = hdr_size + data_in_size, > + .payload_in = pi, > + }; > + > + rc = cxl_internal_send_cmd(cxl_mbox, &mbox_cmd); > + if (rc < 0) > + return rc; > + > + return 0; > +} > +EXPORT_SYMBOL_NS_GPL(cxl_do_maintenance, CXL);
diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c index 30c44ab11347..a6f69864c504 100644 --- a/drivers/cxl/core/mbox.c +++ b/drivers/cxl/core/mbox.c @@ -1084,6 +1084,46 @@ int cxl_set_feature(struct cxl_memdev_state *mds, } EXPORT_SYMBOL_NS_GPL(cxl_set_feature, CXL); +int cxl_do_maintenance(struct cxl_memdev_state *mds, + u8 class, u8 subclass, + void *data_in, size_t data_in_size) +{ + struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox; + struct cxl_memdev_maintenance_pi { + struct cxl_mbox_do_maintenance_hdr hdr; + u8 data[]; + } __packed; + struct cxl_mbox_cmd mbox_cmd; + size_t hdr_size; + int rc = 0; + + struct cxl_memdev_maintenance_pi *pi __free(kfree) = + kmalloc(cxl_mbox->payload_size, GFP_KERNEL); + pi->hdr.op_class = class; + pi->hdr.op_subclass = subclass; + hdr_size = sizeof(pi->hdr); + /* + * Check minimum mbox payload size is available for + * the maintenance data transfer. + */ + if (hdr_size + data_in_size > cxl_mbox->payload_size) + return -ENOMEM; + + memcpy(pi->data, data_in, data_in_size); + mbox_cmd = (struct cxl_mbox_cmd) { + .opcode = CXL_MBOX_OP_DO_MAINTENANCE, + .size_in = hdr_size + data_in_size, + .payload_in = pi, + }; + + rc = cxl_internal_send_cmd(cxl_mbox, &mbox_cmd); + if (rc < 0) + return rc; + + return 0; +} +EXPORT_SYMBOL_NS_GPL(cxl_do_maintenance, CXL); + /** * cxl_enumerate_cmds() - Enumerate commands for a device. * @mds: The driver data for the operation diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index e1156ea93fe7..1cd50ada551b 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -531,6 +531,7 @@ enum cxl_opcode { CXL_MBOX_OP_GET_SUPPORTED_FEATURES = 0x0500, CXL_MBOX_OP_GET_FEATURE = 0x0501, CXL_MBOX_OP_SET_FEATURE = 0x0502, + CXL_MBOX_OP_DO_MAINTENANCE = 0x0600, CXL_MBOX_OP_IDENTIFY = 0x4000, CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100, CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101, @@ -907,6 +908,19 @@ struct cxl_mbox_set_feat_hdr { u8 rsvd[9]; } __packed; +/* + * Perform Maintenance CXL 3.1 Spec 8.2.9.7.1 + */ + +/* + * Perform Maintenance input payload + * CXL rev 3.1 section 8.2.9.7.1 Table 8-102 + */ +struct cxl_mbox_do_maintenance_hdr { + u8 op_class; + u8 op_subclass; +} __packed; + int cxl_internal_send_cmd(struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *cmd); int cxl_dev_state_identify(struct cxl_memdev_state *mds); @@ -984,4 +998,7 @@ int cxl_set_feature(struct cxl_memdev_state *mds, const uuid_t feat_uuid, u8 feat_version, void *feat_data, size_t feat_data_size, u8 feat_flag); +int cxl_do_maintenance(struct cxl_memdev_state *mds, + u8 class, u8 subclass, + void *data_in, size_t data_in_size); #endif /* __CXL_MEM_H__ */