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Tue, 29 Oct 2024 16:44:28 -0700 (PDT) From: Deepak Gupta Date: Tue, 29 Oct 2024 16:44:05 -0700 Subject: [PATCH v7 05/32] riscv: Call riscv_user_isa_enable() only on the boot hart MIME-Version: 1.0 Message-Id: <20241029-v5_user_cfi_series-v7-5-2727ce9936cb@rivosinc.com> References: <20241029-v5_user_cfi_series-v7-0-2727ce9936cb@rivosinc.com> In-Reply-To: <20241029-v5_user_cfi_series-v7-0-2727ce9936cb@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Samuel Holland , Andrew Jones , Conor Dooley , Deepak Gupta X-Mailer: b4 0.14.0 X-Rspam-User: X-Rspamd-Queue-Id: 1252318000B X-Rspamd-Server: rspam01 X-Stat-Signature: zwb914rmqwr9sphf5e8b6ocztbxei3zj X-HE-Tag: 1730245444-695110 X-HE-Meta: U2FsdGVkX1+y7WkfEOkNv1U2HR8j+KFUZs5Bua+jRtJ89FXaSdxYbaFqKq+uiks8tGcg8SXSm/EFvbT2QcxDRmWz7I7A0jbBiYZxModiFaX2j33rnhBGl3VA/g6ZBLr+7dFx1hLUcGij913jKRBHfKkZaP12CCDc/viYrl/iBiIgD4Y70+p95xmWuwobmGpbtMUU/QwHQiVU9ZwQBpy86z+7kgtF4VwxxtoxgJyLLJ1gQWS7c/QmCF6cMBn5tgjC1pKrLAKkgM9sYwA9V/DFjyzj6xY8YCPt6lkGelP0hqL+KUvQgNNigkK7gxxLwExm80x16h4Pira7OcAC6kQ+aGmeIZJgF59JCR6Kl1xl0kzSTENRumgHk+pdA1lPfE75vqXnpOaQs93FlUMyRjEpEte6S0GLO+bebo5KCt6pR9zIvtTm5nU0sJToQxvfluHX3br/2B9Fw6kz/ekgyxsZj57HWqhPATXLxNiOci2YUFoe+VfgBAK7nOQrc9ONkAJDbhauWCKihCfqg/zVKE0RJan39ETRoNz6BFHwc0O1CBEk6hRvdhpW2JKf2Gm+UQ76NZK4r45qX9XtDBSf/qfdBAKwutgzx78tjhw08K/e6hSOQOneuCjxJi8E9dmXaQeh+l11NLi+skYNsHB++CjR1ErmdvLImUXHEi/qlnzQjwFIt6pCL3rX0sYPepCykvONYNBM9D8XiKelrt/tYedIhzQtQYAPkDE4kz3Jm4TpJRbKgVmePZ9e0pZDjYE1IVz11PfHzNuw3x0/lmbyotPf6d9bUBf2NlLkm8qlFrEwhp4Hrf0Y4KcjoF2M1GDFsx58ZdjNW+Wqu8i8hUmukxUq16NU8EBkNqca4tJeRa0CrsVtAwucZp2FLv+fHu0uHVzOLoWxVxlGQ3MW6q1GKVVNDnzHJDIMclbzrMXaKGgWdIh9plTH0Mzejir7DT4av74nCuyk8zz8cvSqzmImpz/ P5Y1VDXT qjKMEvOuFVvCI4oWx6eaLeYKrIhm+BZ/BGvPzMt9EUGFZ88uf8S/1lUvLDgO4fAMqyL0SMIOBB/Oa911nIAw+siB0mm/C9Et7IP0jqo2yhXEIgLA3MI0aw3pXZNLIteTY5wKhx1AqBcPG23DlmXcyANs7SUQQYHK5LJfiraUZqKUvm+CEfIq52OfyuCXwLUm1eP5htP38UVNLHMSFslcWKcqL5QYtyjXMl60eT9vPBYBL0yMle+LRpzqcHiweUNsDhmwJHUOjflF6LQvPPebecn4zNPOvystsLObr14Gdx4wRGEGsbt+jygSuaYgbs2PqHJRQi8wBP98aqkCFNeJBMKB/u6FFah916qxV7GuaM8Jy+7jNbH/iKhDCl0EwCZ6H/IAkZ1qzItjtM0kr+EssA16A8Z/O0kfv49d2aEInW+1Xg/bMkAcLVX7csDijPGEB15P8/6uosK8DU7mh7Nv5sVLUiJpVbnzSTWSuXsxg0/nrB7sI/lgJs5/uYAlWnXgF+caytULj9spkOhh6va1Z8BEyOmjEZoEHVzq/EBBBzGpXEo9vJYPSBJKc9+NFKDJPSonRC5yZfad9qp8CL60i0njstj8I37n3yWVs9VbvpV3Kty41AteWRsfiGy7U6Soj2gOMsjb93dm1VKr/1x3Qv29catoSpCyClnCBYU+fQnKeS5WPWbGkrgicQA== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: From: Samuel Holland Now that the [ms]envcfg CSR value is maintained per thread, not per hart, riscv_user_isa_enable() only needs to be called once during boot, to set the value for the init task. This also allows it to be marked as __init. Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley Reviewed-by: Deepak Gupta Signed-off-by: Samuel Holland --- arch/riscv/include/asm/cpufeature.h | 2 +- arch/riscv/kernel/cpufeature.c | 4 ++-- arch/riscv/kernel/smpboot.c | 2 -- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 45f9c1171a48..ce9a995730c1 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -31,7 +31,7 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); /* Per-cpu ISA extensions. */ extern struct riscv_isainfo hart_isa[NR_CPUS]; -void riscv_user_isa_enable(void); +void __init riscv_user_isa_enable(void); #define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size, _validate) { \ .name = #_name, \ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 27bafc5dd62d..b3a057c36996 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -920,12 +920,12 @@ unsigned long riscv_get_elf_hwcap(void) return hwcap; } -void riscv_user_isa_enable(void) +void __init riscv_user_isa_enable(void) { if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOZ)) current->thread.envcfg |= ENVCFG_CBZE; else if (any_cpu_has_zicboz) - pr_warn_once("Zicboz disabled as it is unavailable on some harts\n"); + pr_warn("Zicboz disabled as it is unavailable on some harts\n"); } #ifdef CONFIG_RISCV_ALTERNATIVE diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 0f8f1c95ac38..e36d20205bd7 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -233,8 +233,6 @@ asmlinkage __visible void smp_callin(void) numa_add_cpu(curr_cpuid); set_cpu_online(curr_cpuid, true); - riscv_user_isa_enable(); - /* * Remote cache and TLB flushes are ignored while the CPU is offline, * so flush them both right now just in case.