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Mon, 11 Nov 2024 12:54:07 -0800 (PST) From: Deepak Gupta Date: Mon, 11 Nov 2024 12:53:50 -0800 Subject: [PATCH v8 05/29] riscv: zicfiss / zicfilp extension csr and bit definitions MIME-Version: 1.0 Message-Id: <20241111-v5_user_cfi_series-v8-5-dce14aa30207@rivosinc.com> References: <20241111-v5_user_cfi_series-v8-0-dce14aa30207@rivosinc.com> In-Reply-To: <20241111-v5_user_cfi_series-v8-0-dce14aa30207@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta X-Mailer: b4 0.14.0 X-Rspam-User: X-Rspamd-Queue-Id: 164BC80018 X-Rspamd-Server: rspam11 X-Stat-Signature: scfh9zf5mfz8juiz9uxd3suts9ybro4a X-HE-Tag: 1731358371-252285 X-HE-Meta: U2FsdGVkX18bHk6bhgM5HOnvSBTCZDYQ4Z5ihU4Qf2OND3O2v4mo8Z2mSESvU1vm+R/RfO+bfcPWhxWO34vYfCY08MK3xbXLN8vrHNNoJyvmaG4dmfTzZBK/Vzj/HkgXaJvjir9h5lTDNhZEYJNud0NZfKBLJXzAXr7hasiwrMKXBt3gDN+bTo1ifYz+cDLHGpuCmEa0Xz5IxA0WIEY/BNHPjl9wkpNDzQD70xirQ/YePZnX/exArd/YYCW/8ku6x4xF0ty3HZSCRmOWs0ovsLPPoQmQ7iNXJ1Y1w5A7cGVGnBeC11tg4CQ5O8PZFZYFLC17NjbX1mMBKNi9r+4nGM177v0SUp405ePvoKBkhp4rKAalxQ0rnht03QLqunYwOUoAS1HqP7Cr4uLUo7p/HgHkqk6OKSbhiVggsVrCEUP1RsUROMD1/WiHXlSZLrPS3LJ68Thf/A0hvy3vnuJjCetdL3zpSxh7lIQLmtGG/SEaExlIrL3n20X/yEJtkCzjgPawxfKOSlfdYtDk0hdEOTjXmIcYLF0GveAukP0i4eKPeFEgcmKwUJGKqfUgCfBrmrHuV7W/LcIdbaBdbZ7ymCae34LzdnoHlakGli+hUtd502EIWDWXk8mb3cZoGodiYTWCGFbSSJC/kpfG4xGR2FRlYtGfuKFF+DZjHLt3hXkuBtffp2OLazcmgdwOZG6QIZuH/e3WK7wYX4LD+blaXtoucAX9v3D7fwqvyyCKobg4VM+qUwuyBrD6jC4uxIPmrvA6Lu52IxnrTD9pbV97ZF8ice0RltV7q3VaryK7Yl4kgnDk5jVrst+0cmZm6b9AyGdnUQqJL9VrKASgiW8kGVQ/JJSkAbJTVWZtwJNFhcaJhttvQjkawL+iapVZlNfrU4Kv0G6l+fQH2GGLFDnY4JLFKs/+bfAvV5M2QQ6jjVGFu8GD7nzLbu/x83IHPqWvLdZRtR0LTkrqkDZBlrj tumxIc6O UP/I/MrBPwoNFsuR4bbi3qOQXENWZFaYS39PY9ird1iRwk7GtcqJ+4k//9Mfi0W7hQX0fVjAHf0ad4p702hdwqxpTQocDtj/7kzw9V3s70m49ZyHXDxLoDCsb4dK9Lvne5jDhRsmyvOqhxkWnOHT98OWb+3hdDcP0SGETnGdr6e2prTMeZgxM4aTG75WBe9lQgzXYxefy7oip+VtQ74yUi4NOjN4AhkvilXu51QECKwgd7mokcQFoCaDTYzs8ddlVW/B1RUluqVXH4084HH2HLm1O1RoMF+0+KJLq1wFU744CMqprP8eaBdnnC2qRZlUihicBeuwSJfpmqcZqvFwx3siLA5p8nF/umKurEaRGkR59CU5gmLuHZ62/63xSEQ6gEq2D5JBar2+IxXJ77+Fv160/MJJ8SHH5Dm0KlpjJSwzw1GKvLCWWaFs3mgGJjFYqGpy5Whob7MLdU5I5LoT8gr1uV0TwZZWJn5pLNM8niKvfrEbpepWOoCZ9kkesQRzPtlZ1 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: zicfiss and zicfilp extension gets enabled via b3 and b2 in *envcfg CSR. menvcfg controls enabling for S/HS mode. henvcfg control enabling for VS while senvcfg controls enabling for U/VU mode. zicfilp extension extends *status CSR to hold `expected landing pad` bit. A trap or interrupt can occur between an indirect jmp/call and target instr. `expected landing pad` bit from CPU is recorded into xstatus CSR so that when supervisor performs xret, `expected landing pad` state of CPU can be restored. zicfiss adds one new CSR - CSR_SSP: CSR_SSP contains current shadow stack pointer. Signed-off-by: Deepak Gupta Reviewed-by: Charlie Jenkins --- arch/riscv/include/asm/csr.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index fe5d4eb9adea..e07b55028cc0 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -18,6 +18,15 @@ #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ +/* zicfilp landing pad status bit */ +#define SR_SPELP _AC(0x00800000, UL) +#define SR_MPELP _AC(0x020000000000, UL) +#ifdef CONFIG_RISCV_M_MODE +#define SR_ELP SR_MPELP +#else +#define SR_ELP SR_SPELP +#endif + #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ #define SR_FS_OFF _AC(0x00000000, UL) #define SR_FS_INITIAL _AC(0x00002000, UL) @@ -205,6 +214,8 @@ #define ENVCFG_PMM_PMLEN_16 (_AC(0x3, ULL) << 32) #define ENVCFG_CBZE (_AC(1, UL) << 7) #define ENVCFG_CBCFE (_AC(1, UL) << 6) +#define ENVCFG_LPE (_AC(1, UL) << 2) +#define ENVCFG_SSE (_AC(1, UL) << 3) #define ENVCFG_CBIE_SHIFT 4 #define ENVCFG_CBIE (_AC(0x3, UL) << ENVCFG_CBIE_SHIFT) #define ENVCFG_CBIE_ILL _AC(0x0, UL) @@ -223,6 +234,11 @@ #define SMSTATEEN0_HSENVCFG (_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT) #define SMSTATEEN0_SSTATEEN0_SHIFT 63 #define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT) +/* + * zicfiss user mode csr + * CSR_SSP holds current shadow stack pointer. + */ +#define CSR_SSP 0x011 /* mseccfg bits */ #define MSECCFG_PMM ENVCFG_PMM