From patchwork Mon Dec 23 02:55:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13918386 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EBFEE7718D for ; Mon, 23 Dec 2024 03:03:15 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id A91446B007B; Sun, 22 Dec 2024 22:03:14 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id A1A9D6B0083; Sun, 22 Dec 2024 22:03:14 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 8E1846B0088; Sun, 22 Dec 2024 22:03:14 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0017.hostedemail.com [216.40.44.17]) by kanga.kvack.org (Postfix) with ESMTP id 68D116B007B for ; Sun, 22 Dec 2024 22:03:14 -0500 (EST) Received: from smtpin22.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay01.hostedemail.com (Postfix) with ESMTP id EB8C81C842C for ; Mon, 23 Dec 2024 03:03:13 +0000 (UTC) X-FDA: 82924726374.22.E2F0BAA Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) by imf22.hostedemail.com (Postfix) with ESMTP id 58AD7C0003 for ; Mon, 23 Dec 2024 03:02:33 +0000 (UTC) Authentication-Results: imf22.hostedemail.com; dkim=none; spf=pass (imf22.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com; dmarc=none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1734922974; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5mFp+SLkTnIkXhQJVf0IJxxiIUoX5aYBaDbaTcw7+1I=; b=jS9GONuLUX8RvYLBiYV6EcXyKy95P24I/dpYViihuyiXUKZQr+9vZuIuDfj8E5+3kqZcKA ZW2Gg8XUq/5h4s+lgKlU34PdlXiZNUlIqjYvoK4X8VvGBzs1yzYQk2lYww4oWgRjFmXZQ8 grEEERPCgMSAEd4Fl55gkUorj88BjFc= ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1734922974; a=rsa-sha256; cv=none; b=EXD8zzQ3Y4axqwYG6P4pqEv646oadcGLIs1+syOWxhRr0wp5i7zzm5eYoNfARsZ56iYm/g foxuoKbRwYMD3oVbzYgxiBy5Bfst4qaIctG7m1bqr9ZFo2jLsgHv+bZ/FtN8tV+xEruN0D mbxsDg6t81PTapxuOBRkIWE0cQrzI4k= ARC-Authentication-Results: i=1; imf22.hostedemail.com; dkim=none; spf=pass (imf22.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com; dmarc=none Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tPYdq-000000001Ih-0scS; Sun, 22 Dec 2024 21:57:58 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 10/11] x86/mm: enable AMD translation cache extensions Date: Sun, 22 Dec 2024 21:55:16 -0500 Message-ID: <20241223025751.3268975-11-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241223025751.3268975-1-riel@surriel.com> References: <20241223025751.3268975-1-riel@surriel.com> MIME-Version: 1.0 X-Rspamd-Server: rspam10 X-Rspamd-Queue-Id: 58AD7C0003 X-Stat-Signature: r48dxqk633crdxspxodpgm5jyztercyd X-Rspam-User: X-HE-Tag: 1734922953-558361 X-HE-Meta: U2FsdGVkX1/D/EgZcV0ah9+SGy8wB7XJVGYpfe0Lw7iAUc39KB4JyewZseuYHLxrqRZc/sHeiAXBMx/ssGMDfhvv0jnbRwF+oGwFF5XQ+pwEECL36MMSy0T4rfLmCAns1mETtLvm8KtK1CZfutH0hCUwflFX3AucDB2mjssCGo8XZhMFvk3WO3aAzZCz9zg9Dwf0bEeq5MSbmJBBCNk1w8AT3e7UmC8iofm4PPiaMukJuzYTCYH5ErnaDj4PxUe3UEODltZyx8wW5QEDucIqKTgqXsjvdHe7UTv8EFFHgNZ27F63/0w2unTU1F3Y575ubfaworGpF0j2pBlJDN98O4/TCqF5rEMPmzrAvzKTmnQYgq8lmbPtRl6dUOuZA02cUg5ogmsWfugG05HkeA2WZOfcPvmFmFZpLrlfyFZ9e9BoeHGPj48sb90VRudaoZqN2w9wCliRBp9iW7/ZTYsYfpOWSU6BXTXS83Q2bqarGDBBKo3VKzJnYfzhUbGugCIztFjQ18ZKJuU8T6KKoZJgEnhFlEJjGUOCUHsVUJuPuBNyH7yOtX/mP7e9S6zBVST7UtO6YThph2BkOr2dpJL6P+HtE/E5YERHu9VoPF02EslERDsu1SoIwErsu1B7oYW4yhZTxlv+1BhH65PxAOLVmqquzjIkTQN9VtyDZP1/IpWUZuG9AQ2srfGwbQsjrjQerlFig5H7AOOD+0mASHDb7mP/Zfb2kjzwdIqHglu54eEAnE1w1ph5MTcOkkcZoSi7E9sGxMzp6/hWdy9Na8Qy90M9YxZpkj8hORvck5Kjv2Az1updinP2DhVPyM30Y8/PvLsHpgwdsSqnC1QbDzQU9vFZYzEucDDeGX4qOhikDGii9SbFe6KTxpo84DIeXAonrIM1hs9v+KuQUiBe/R6wQw9WLehMRZHWm9WW1gGLCNBTMzSLDQRZRIwWKZCpQX6KbN1/bVhQBuxBpQI8Jgi 8jM/esr/ QmPMJEqmZ3re1fJcyzaUSKeRsbMvoRPEAGxiA78j2+Hj6hNl7iW/u/FS463xeI1kaHW055BIr0Y4BpOumo9hIwQMcZwILnyFWIDoHvYAobBKJMjfj+oGxZQNVnpXlz/fZZeIfEqwvZw/PN4dCq2wwHqu4W+OCs5MbfMv4i+BNMQaEiimBPuPDYHCWJZ8lTqdwjIonSCwbYXRb9g1V+gKx2x+lDCvM21+dnZKVUJsEsTUPA9ysJqZFTelretgMBDhqjWNTaF3ZbKMBFBrdIrkUW48sFaslYmioR5bdpCowNqgfpOYPCQpVKXG/whtHeT12dkXG X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: With AMD TCE (translation cache extensions) only the intermediate mappings that cover the address range zapped by INVLPG / INVLPGB get invalidated, rather than all intermediate mappings getting zapped at every TLB invalidation. This can help reduce the TLB miss rate, by keeping more intermediate mappings in the cache. From the AMD manual: Translation Cache Extension (TCE) Bit. Bit 15, read/write. Setting this bit to 1 changes how the INVLPG, INVLPGB, and INVPCID instructions operate on TLB entries. When this bit is 0, these instructions remove the target PTE from the TLB as well as all upper-level table entries that are cached in the TLB, whether or not they are associated with the target PTE. When this bit is set, these instructions will remove the target PTE and only those upper-level entries that lead to the target PTE in the page table hierarchy, leaving unrelated upper-level entries intact. Signed-off-by: Rik van Riel --- arch/x86/kernel/cpu/amd.c | 8 ++++++++ arch/x86/mm/tlb.c | 10 +++++++--- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 226b8fc64bfc..4dc42705aaca 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1143,6 +1143,14 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) /* Max number of pages INVLPGB can invalidate in one shot */ invlpgb_count_max = (edx & 0xffff) + 1; + + /* If supported, enable translation cache extensions (TCE) */ + cpuid(0x80000001, &eax, &ebx, &ecx, &edx); + if (ecx & BIT(17)) { + u64 msr = native_read_msr(MSR_EFER);; + msr |= BIT(15); + wrmsrl(MSR_EFER, msr); + } } static const struct cpu_dev amd_cpu_dev = { diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index c5459516a72e..f1e2358616e5 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -480,7 +480,7 @@ static void broadcast_tlb_flush(struct flush_tlb_info *info) if (info->stride_shift > PMD_SHIFT) maxnr = 1; - if (info->end == TLB_FLUSH_ALL) { + if (info->end == TLB_FLUSH_ALL || info->freed_tables) { invlpgb_flush_single_pcid(kern_pcid(asid)); /* Do any CPUs supporting INVLPGB need PTI? */ if (static_cpu_has(X86_FEATURE_PTI)) @@ -1113,7 +1113,7 @@ static void flush_tlb_func(void *info) * * The only question is whether to do a full or partial flush. * - * We do a partial flush if requested and two extra conditions + * We do a partial flush if requested and three extra conditions * are met: * * 1. f->new_tlb_gen == local_tlb_gen + 1. We have an invariant that @@ -1140,10 +1140,14 @@ static void flush_tlb_func(void *info) * date. By doing a full flush instead, we can increase * local_tlb_gen all the way to mm_tlb_gen and we can probably * avoid another flush in the very near future. + * + * 3. No page tables were freed. If page tables were freed, a full + * flush ensures intermediate translations in the TLB get flushed. */ if (f->end != TLB_FLUSH_ALL && f->new_tlb_gen == local_tlb_gen + 1 && - f->new_tlb_gen == mm_tlb_gen) { + f->new_tlb_gen == mm_tlb_gen && + !f->freed_tables) { /* Partial flush */ unsigned long addr = f->start;