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a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1734923024; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yRu48wDyQbjXodzZ0IQCHNm8zDJ9Qrsyu2zd3npGVTA=; b=jtaDcNDO0ttwMomAlUhi3xk3pQHrs1OAT8N/JkaJ6EtMHhPHtA9NIJs7jTDt+ajc3LlOfK skT7u6xmIfTHmkFUjHu3G7ZR1qVavBtVCto4fxKobxHzFArzleeqHbd6dSsLl5QgSKhUFB 7o3S/RYkkWKWCPgNZkLtL7mwnAxqCKE= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tPYdp-000000001Ih-079E; Sun, 22 Dec 2024 21:57:57 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, linux-mm@kvack.org, Rik van Riel Subject: [PATCH 04/11] x86/mm: add INVLPGB support code Date: Sun, 22 Dec 2024 21:55:10 -0500 Message-ID: <20241223025751.3268975-5-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20241223025751.3268975-1-riel@surriel.com> References: <20241223025751.3268975-1-riel@surriel.com> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Server: rspam03 X-Rspamd-Queue-Id: 9D8A9180005 X-Stat-Signature: u77ehgc7r8o7eu51o6cfcyhbbpxc1hm4 X-HE-Tag: 1734923015-385042 X-HE-Meta: U2FsdGVkX19WByLthZ7VViBtTAyhVk6UlgjgTfJIBCKMfgGON3JxMRMSiUOKbhOTIM72jCTAlszuSIzsP+ymnvZZqOgW5WPryHbiaCM6D1KU1wbz92RTPE9+ULVua9qJX3cxoNkoqqr8zXN4IEDlb5zoyw9vhu1UMoN6xIu658L+P8WQVhorw4OTGKRCpqXujjE8xO83M0BcYa41e6c/gybcXn2age+RI6Y+8ArtnYSl5IOlGQhcAlZw8duZtuznMITbV/JEGfKuRz2iUniJyGVg7kVdAiQa/o+GNtdg9nIaZgTBF7j05hLNFSnxXrDNehifKriXJPvSJjhZAbp5V1KV8Yohrf+A/Fb1a2NX2aPe/JJyy+wPs1GtXbfXRuBTnyGYTqpzDGaM2puzSG5kPk6edab1HislmuxRBkudOIhhSzl2m5CS4lrvutzbaj30nxjcxIR6aveZZ0EnosNFm+1lYMYuPJASBPLfyUcbRw2eWR+PzjVyySCi8L4yOhFSeCQEjQuPWPhh4KCH/Th9+MAoc0b8F1DLssABnGUpXNhAZQ/Y/yLtBupwJaGDQlF7Gu5zq7BedhdWZdmzvGUmvxqcOA2jX+JzHGw3VRphFW94jDxYFKZzrOOx3Clxg519IpoI0e90v1AcYkBCSKjQXHxvhbHQk74MhoztBQ0SOZ/EotShc9HJQRp6LMnGX+kqEi/aTv9Y4lUAkSK+oZTb3BQLL/Wp9xgCKwGYx4kWvdhFK/CW6ZyUicPRFHQhRZfQY0/OsQHTJLMjqcSHpo/iVPbrVP67moNX8byicvv9OH0ea6NGhBQXXhT4kPJl1HzndCIyupirkN+fU8U2GyiYVyuCrkgzpoWEJBIGNGXjomeb3fO9iHrb4GLt8JboGjmQenFyAR7WTCuZozg7fr0kMhtqfT/wfRMfvgN5g5ZwMGlPXIAD68ZCwRgA7aB9qFS1gYF34VaR1y06kZq0SB5 uFs7xqzO Bx5/tpkhJBwuiP52Na73Bfs7x0E5BzZrUxOV907UGk/Sf7tqE5Z4OPOfGCCtZ0ByzqghfLqTC3YXJ6Kuzh7zS5+4K1IO2d952n8P0i6q1sMwQFbpU0V+YuIbRryI0garjE480oGbluCNnQve1PkALCdmJSm6ROfHargw2RMr18+D7S1Oyuygo1XmbDnfnKxAZLeX3y/d1ORtws7t6JdaifsAWGIkZN6Zm6LlmxqW9Lhcnshlf6NRHJ9S4s9NfNxK9VNivSAkhDUA/6ZgV2Ah9Y8u7w7iRhugzAVA/K+SqPtLl3knWnigVl2l2kJM9QSLaxxQ4 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Add invlpgb.h with the helper functions and definitions needed to use broadcast TLB invalidation on AMD EPYC 3 and newer CPUs. Signed-off-by: Rik van Riel --- arch/x86/include/asm/invlpgb.h | 93 +++++++++++++++++++++++++++++++++ arch/x86/include/asm/tlbflush.h | 1 + 2 files changed, 94 insertions(+) create mode 100644 arch/x86/include/asm/invlpgb.h diff --git a/arch/x86/include/asm/invlpgb.h b/arch/x86/include/asm/invlpgb.h new file mode 100644 index 000000000000..862775897a54 --- /dev/null +++ b/arch/x86/include/asm/invlpgb.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_INVLPGB +#define _ASM_X86_INVLPGB + +#include + +/* + * INVLPGB does broadcast TLB invalidation across all the CPUs in the system. + * + * The INVLPGB instruction is weakly ordered, and a batch of invalidations can + * be done in a parallel fashion. + * + * TLBSYNC is used to ensure that pending INVLPGB invalidations initiated from + * this CPU have completed. + */ +static inline void __invlpgb(unsigned long asid, unsigned long pcid, unsigned long addr, + int extra_count, bool pmd_stride, unsigned long flags) +{ + u64 rax = addr | flags; + u32 ecx = (pmd_stride << 31) | extra_count; + u32 edx = (pcid << 16) | asid; + + asm volatile("invlpgb" : : "a" (rax), "c" (ecx), "d" (edx)); +} + +/* + * INVLPGB can be targeted by virtual address, PCID, ASID, or any combination + * of the three. For example: + * - INVLPGB_VA | INVLPGB_INCLUDE_GLOBAL: invalidate all TLB entries at the address + * - INVLPGB_PCID: invalidate all TLB entries matching the PCID + * + * The first can be used to invalidate (kernel) mappings at a particular + * address across all processes. + * + * The latter invalidates all TLB entries matching a PCID. + */ +#define INVLPGB_VA BIT(0) +#define INVLPGB_PCID BIT(1) +#define INVLPGB_ASID BIT(2) +#define INVLPGB_INCLUDE_GLOBAL BIT(3) +#define INVLPGB_FINAL_ONLY BIT(4) +#define INVLPGB_INCLUDE_NESTED BIT(5) + +/* Flush all mappings for a given pcid and addr, not including globals. */ +static inline void invlpgb_flush_user(unsigned long pcid, + unsigned long addr) +{ + __invlpgb(0, pcid, addr, 0, 0, INVLPGB_PCID | INVLPGB_VA); +} + +static inline void invlpgb_flush_user_nr(unsigned long pcid, unsigned long addr, + int nr, bool pmd_stride) +{ + __invlpgb(0, pcid, addr, nr - 1, pmd_stride, INVLPGB_PCID | INVLPGB_VA); +} + +/* Flush all mappings for a given ASID, not including globals. */ +static inline void invlpgb_flush_single_asid(unsigned long asid) +{ + __invlpgb(asid, 0, 0, 0, 0, INVLPGB_ASID); +} + +/* Flush all mappings for a given PCID, not including globals. */ +static inline void invlpgb_flush_single_pcid(unsigned long pcid) +{ + __invlpgb(0, pcid, 0, 0, 0, INVLPGB_PCID); +} + +/* Flush all mappings, including globals, for all PCIDs. */ +static inline void invlpgb_flush_all(void) +{ + __invlpgb(0, 0, 0, 0, 0, INVLPGB_INCLUDE_GLOBAL); +} + +/* Flush addr, including globals, for all PCIDs. */ +static inline void invlpgb_flush_addr(unsigned long addr, int nr) +{ + __invlpgb(0, 0, addr, nr - 1, 0, INVLPGB_INCLUDE_GLOBAL); +} + +/* Flush all mappings for all PCIDs except globals. */ +static inline void invlpgb_flush_all_nonglobals(void) +{ + __invlpgb(0, 0, 0, 0, 0, 0); +} + +/* Wait for INVLPGB originated by this CPU to complete. */ +static inline void tlbsync(void) +{ + asm volatile("tlbsync"); +} + +#endif /* _ASM_X86_INVLPGB */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 7d1468a3967b..20074f17fbcd 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include