From patchwork Thu Jan 16 02:30:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13941157 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0534DC02180 for ; Thu, 16 Jan 2025 02:32:47 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 7667C6B0082; Wed, 15 Jan 2025 21:32:47 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 716FF6B0085; Wed, 15 Jan 2025 21:32:47 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 5DEE1280001; Wed, 15 Jan 2025 21:32:47 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0014.hostedemail.com [216.40.44.14]) by kanga.kvack.org (Postfix) with ESMTP id 3A80B6B0082 for ; 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b=y/7OxsQsWMjIcfdw1XxNGfYnAvIFjNLcdHhKnombWb3JHkZ9IrZZP6yfpXC8GVZKuY45eE pJ2tVk2/5B7lPWjDBm3Em6FWcjlKN+aQy4imtDyHqYtkaNCgDvmtpQW63GHpwlymYLTHlm VmaWqeIcI6p1xZWSGwyAZ7as2cRcPrI= ARC-Authentication-Results: i=1; imf27.hostedemail.com; dkim=none; spf=pass (imf27.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com; dmarc=none ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1736994765; a=rsa-sha256; cv=none; b=0qDmMqdGl9J5vmyCO74LjVq7NX/xI06xx3X4Bqf73x2YmdXbsqdwBXuHsa/0pfcUkIgWrn E0U+dVOByPMkVrHeHg7z49xEB4G7F6kbPeM4TkEAUoeFRJJ2M4KMG+4VJwg7lAM1wnBfHc ut8Tc1gomFzaNccZJ57axEoQ54/bXDk= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tYFfO-000000003nd-3pb4; Wed, 15 Jan 2025 21:31:30 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Rik van Riel Subject: [PATCH v5 10/12] x86,tlb: do targeted broadcast flushing from tlbbatch code Date: Wed, 15 Jan 2025 21:30:33 -0500 Message-ID: <20250116023127.1531583-11-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250116023127.1531583-1-riel@surriel.com> References: <20250116023127.1531583-1-riel@surriel.com> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Server: rspam09 X-Rspamd-Queue-Id: 544B340006 X-Stat-Signature: sxte6rqzpfidzrkhqznuipfcb6d8ehnd X-HE-Tag: 1736994765-497859 X-HE-Meta: U2FsdGVkX19N/XtFdMdSbv6BeG1+XLLkO9Po3fRinmbIgBNwYG9O+F8jwpOW+1AUpNFJkCtWbHiOA+RQUX2uC+ZUQ8H1Bf7t06tmiNFXIy676+h6CL0YUIMGFb1OkAEhDIWXrTXYwz1vviUbSUOMmoz9285pu1L+VFHIU8geM5hqCUEg3H4MZxsVMvtDmnpHWQcz8sbjBJ4va9PxzI9QQgNfOxrMOes6hXSMojMmPjqN5lMQsZxBDv48FA2f+8VDuN0DiPGAjmGRBKEliHDIgWfJ+ZlROFfLSofSm4EZhLBomWlM6T7XGg3W3ZiQ28PXqE4u9tn38Bn+/lZlOuYVeU87AonT3UF2+eEU109Yz7bzKrfbuJE/dDUbj3hM8F0GXAbPFibtJJOzLi/b/FfUh3hqsobLQFyctqB0aTUHqNLsbfFGoq2p8FK/bPc52PlzYV/RtDWteJPXDbhbBZ274u73vbbo5xesRkOaTYYsC4tqrSE0Kj/Jf7zSUa2uzTRoQUaQ7ekPebXbo+abvU822RLlA5hUpx4WblI/YJGDP5dWh4ni345ObVCvNXv7Zq9VPjoBU4mnnfMtiW0vebMEqMf8FR+XbASeHuFcT/5ka2DqCDGG156ofGAY+PJgCt/o9e00+qHQslQVEx8M1tlyxD7sRcqfGwX8E5sFKNoubygH99foWSTT90AaHlr56XTR6ncVdY0Og/OnWRHBqSZBcThKp4yZVwExJ6oydqArF3nL3nQ9Szf6FulAG/x0vOHNwUd3YOkzM/EkNmLmy0hQlDJQvyqLg+79fuu7JLIVKO4fExooV/PxxJyTvl5//H0Sw7s7Ap6yAqQdyL1rpOypLTNNdkCHbxnUHUNf21eyes/gu88zEkKwPw4ZycTAB9WGDA9BOnfZGlSO0UWStxtBBiPo7JWh3gBRS4y7FoF+gmsfa7svQFXyR1U8qfyKzmB1QlPjd+lmK7WqVAdMfc/ shJgpv9l 6HwNqGoVMAO96HH2zDEIkWktLWC9qlyShSsi/UOcpkGLGZvf9ZaMhJCw7gUzGfYm9VfI5aYsZVW2LneAICqvbZXoIoZINX2TVs20rpnNDjlSuYPhiy4tS75sDp8ZHxIyaGzoJ2/lcAOtSnmMSBltDA+1YMUlpSpIJi8FapbK/eiXVDfHd8LZi/iBoPOWYgRw+ZKtjqFotoIuN4bYhJNa0H4v+cx0zRhk44qOA1dHgXeA52+KZb9NsU39pEyxa6QParJzdvGT8eby5f/2uhEV31/GpoVeqyFkt2sO89yVkaDrizVtd8O9MqKvnyifobmlLd8Dr1J4MqlsnuZJIz3fgXAugSuMtqYT9GFM6Ch8FC58flZoUByHLPly7IVpPZWUmSnE3fUOdbxR48CzYAKnUpXT59uf+enYIySLfYi/+1l0EuAA= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Instead of doing a system-wide TLB flush from arch_tlbbatch_flush, queue up asynchronous, targeted flushes from arch_tlbbatch_add_pending. This also allows us to avoid adding the CPUs of processes using broadcast flushing to the batch->cpumask, and will hopefully further reduce TLB flushing from the reclaim and compaction paths. Signed-off-by: Rik van Riel --- arch/x86/include/asm/tlbbatch.h | 1 + arch/x86/include/asm/tlbflush.h | 12 ++------ arch/x86/mm/tlb.c | 54 +++++++++++++++++++++++++++++++-- 3 files changed, 55 insertions(+), 12 deletions(-) diff --git a/arch/x86/include/asm/tlbbatch.h b/arch/x86/include/asm/tlbbatch.h index 1ad56eb3e8a8..f9a17edf63ad 100644 --- a/arch/x86/include/asm/tlbbatch.h +++ b/arch/x86/include/asm/tlbbatch.h @@ -10,6 +10,7 @@ struct arch_tlbflush_unmap_batch { * the PFNs being flushed.. */ struct cpumask cpumask; + bool used_invlpgb; }; #endif /* _ARCH_X86_TLBBATCH_H */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 5eae5c1aafa5..e5516afdef7d 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -358,21 +358,15 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm) return atomic64_inc_return(&mm->context.tlb_gen); } -static inline void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, - struct mm_struct *mm, - unsigned long uaddr) -{ - inc_mm_tlb_gen(mm); - cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm)); - mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL); -} - static inline void arch_flush_tlb_batched_pending(struct mm_struct *mm) { flush_tlb_mm(mm); } extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch); +extern void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, + struct mm_struct *mm, + unsigned long uaddr); static inline bool pte_flags_need_flush(unsigned long oldflags, unsigned long newflags, diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index bfc69ae4ea40..81f847c94321 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -1659,9 +1659,7 @@ void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) * a local TLB flush is needed. Optimize this use-case by calling * flush_tlb_func_local() directly in this case. */ - if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) { - invlpgb_flush_all_nonglobals(); - } else if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) { + if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) { flush_tlb_multi(&batch->cpumask, info); } else if (cpumask_test_cpu(cpu, &batch->cpumask)) { lockdep_assert_irqs_enabled(); @@ -1670,12 +1668,62 @@ void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) local_irq_enable(); } + /* + * If we issued (asynchronous) INVLPGB flushes, wait for them here. + * The cpumask above contains only CPUs that were running tasks + * not using broadcast TLB flushing. + */ + if (cpu_feature_enabled(X86_FEATURE_INVLPGB) && batch->used_invlpgb) { + tlbsync(); + migrate_enable(); + batch->used_invlpgb = false; + } + cpumask_clear(&batch->cpumask); put_flush_tlb_info(); put_cpu(); } +void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, + struct mm_struct *mm, + unsigned long uaddr) +{ + if (static_cpu_has(X86_FEATURE_INVLPGB) && mm_global_asid(mm)) { + u16 asid = mm_global_asid(mm); + /* + * Queue up an asynchronous invalidation. The corresponding + * TLBSYNC is done in arch_tlbbatch_flush(), and must be done + * on the same CPU. + */ + if (!batch->used_invlpgb) { + batch->used_invlpgb = true; + migrate_disable(); + } + invlpgb_flush_user_nr_nosync(kern_pcid(asid), uaddr, 1, false); + /* Do any CPUs supporting INVLPGB need PTI? */ + if (static_cpu_has(X86_FEATURE_PTI)) + invlpgb_flush_user_nr_nosync(user_pcid(asid), uaddr, 1, false); + + /* + * Some CPUs might still be using a local ASID for this + * process, and require IPIs, while others are using the + * global ASID. + * + * In this corner case we need to do both the broadcast + * TLB invalidation, and send IPIs. The IPIs will help + * stragglers transition to the broadcast ASID. + */ + if (READ_ONCE(mm->context.asid_transition)) + goto also_send_ipi; + } else { +also_send_ipi: + inc_mm_tlb_gen(mm); + cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm)); + } + mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL); +} + /* * Blindly accessing user memory from NMI context can be dangerous * if we're in the middle of switching the current user task or