From patchwork Thu Jan 16 02:30:27 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13941162 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53EC3C02183 for ; Thu, 16 Jan 2025 02:32:58 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 015266B0089; Wed, 15 Jan 2025 21:32:49 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id EBAC06B0093; Wed, 15 Jan 2025 21:32:48 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id AEF5C6B0089; Wed, 15 Jan 2025 21:32:48 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0015.hostedemail.com [216.40.44.15]) by kanga.kvack.org (Postfix) with ESMTP id 6F80C280001 for ; Wed, 15 Jan 2025 21:32:48 -0500 (EST) Received: from smtpin06.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay03.hostedemail.com (Postfix) with ESMTP id 28A2FA0598 for ; Thu, 16 Jan 2025 02:32:48 +0000 (UTC) X-FDA: 83011742016.06.17E8B98 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) by imf13.hostedemail.com (Postfix) with ESMTP id 96D0020006 for ; Thu, 16 Jan 2025 02:32:46 +0000 (UTC) Authentication-Results: imf13.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf13.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1736994766; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sOiwDzUcJmcySWabyvYzZaW6UaPMP6se+kpAPen0v7I=; b=ooJK56KJ5tq2w4dkpJyhFpqy8Xti1lu6N0/pOQqt3o8H9R70YwgOBoMYxF9E0b5BC3LnyM qk24aieZ/Jbct09uPl583JqDNN3RxDFdPmu42eoMnBVzcnQ+Dx1wWXr59ZKptwJv5mtR9O Piaqkr/mZX5bIV8YWc+UbztBXTsr2mo= ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1736994766; a=rsa-sha256; cv=none; b=BXqARa5uQDYxxVpVQgSeKb5QB0FvnmEeXGa/VDbC5shYB8BS2qlLYYUWIFvJYB1bukfslt NGJuJ4/CmYGB1rYHBxtmspHDzX9uwSMe1ABSCvuLfw/1MbqP6/oztHjfO51dJgKXmMvLEd rfwIEoi3Y8nOZrrTGBCnC+COo/DB02Q= ARC-Authentication-Results: i=1; imf13.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf13.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tYFfO-000000003nd-3FjL; Wed, 15 Jan 2025 21:31:30 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Rik van Riel Subject: [PATCH v5 04/12] x86/mm: get INVLPGB count max from CPUID Date: Wed, 15 Jan 2025 21:30:27 -0500 Message-ID: <20250116023127.1531583-5-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250116023127.1531583-1-riel@surriel.com> References: <20250116023127.1531583-1-riel@surriel.com> MIME-Version: 1.0 X-Stat-Signature: atk5je4za8dmwbccyxyya7w6ixnngwsy X-Rspam-User: X-Rspamd-Queue-Id: 96D0020006 X-Rspamd-Server: rspam03 X-HE-Tag: 1736994766-812024 X-HE-Meta: U2FsdGVkX19+liAaZgqOTAUh2yT/LCyDxcCPJp9u5P7xqpFrwEcuQEKWVTqV1DMxcdtnCAxGlHpJ/ctkmuvKLF6zi0gEGlyNfjELr/Ty6hVgcWfFNmsGfcFncnv6FzsGdcYRLr/JML5zghG2jyOyc4gdkI4Qtwfp2fEA2MC3C18NVYIbeBHKzd+sp8mGEeltz+H4EAdbDghM1PLj/Dyt4GYL66Mj7UUl/eS4XOzhm6q+KEqWb7FeYzXie3OV+bNr6t2xtcbmZl2fe637hRNkgyfS0FU1qvC2IXefLHm9RLvY8nGYRHIqq/H0gF3j+TuiVgq1feyhu0gp2x0hAUs4Wx1VvxacO4AyPDKj3Au++j1aeeYVqswZ75UOOj3sK0W+2+WpfqYfcKmOsATpsAMSSh/50AnKMst80MvIcrvznf0iXQ6tm+VmdJ1EyhMej+V7eQgMoI9bK7h6WEhooYRySIF/wj13U2NjekqI5GPh1c/NwaRUpx1zYGbSnG7m/0EoUG2o+NmSxBJBlNhXMTE9hv7TCjbhmxVv40JRlyCmIrL/KfEv9yhRuH7nCHtogbpH3IdCCC0ZcP/6ROeEq0BOQFkQxmz30RUMPiqxZ67mfbf4GI8XnHZmtx0WnzVS9nSs7s5ecxRxI4wWTqVm0n4HxkEfELw7FAdZz+9L7aON4dp3BDxd6P31YikyLPWYWcthmdd2OkBXafzkTRzOojLEytVdhwwuqe6uRopmzqni07h/E5hcQcl8F5foDBXfP63h3ONlAqdQk2TlPLpwWPMy6sBXcF9tmaWFn30g4siKjLMC+94SHQeGvFDY59BnlheOAqBRQpe9AeAo/c4KALINPglASnQvh1Ek+1Y4/dDmsrumsE8Iy1U+EjbMBUXWfR3KTYjpluIK9EZObtaluhX9viDlqUDOnMtQS8enMtbwk6/4fCjTg+jWtnUgY8temVGTsssI+gYfTbVz++z2zag l1kpdhk7 WXtQOn+U8zbToj4yUH7gmBIVtDV3AZqRVYS+3su5IrFjVc5smSmWNzYCMzVvr+bLK7iRvpDRVV8Vmw12pe115x0wg2ozomfsHpXzh6SXpHcETTchJaCxUPSDRT0TE0Ql1vX8cIynqaCNu79s3zyYYyBpPrV3UWyK4bxesaz5cpCq2GIW/F0gO0t/LD+0s+YyrHReE1s1MXd/hEJL+mWLJs+evgMP5AUheseKYdguQXAnvVIPuz7Mm+kpS5XCHA/o3IfQ4Nr33xP5hK7kvApZb3VZjGW84fkUMo9Lc0rkQcYsXyUcuRkTTUHg3UP0o3hHgPTPjteUlf68BhArcvfSkbDtP5/NdqvjulHSKCJQsuktoakj8NHHBrmlKgQ1CqvzLKHOY X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: The CPU advertises the maximum number of pages that can be shot down with one INVLPGB instruction in the CPUID data. Save that information for later use. Signed-off-by: Rik van Riel --- arch/x86/Kconfig.cpu | 5 +++++ arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/tlbflush.h | 7 +++++++ arch/x86/kernel/cpu/amd.c | 8 ++++++++ 4 files changed, 21 insertions(+) diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 2a7279d80460..bacdc502903f 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -395,6 +395,10 @@ config X86_VMX_FEATURE_NAMES def_bool y depends on IA32_FEAT_CTL +config X86_BROADCAST_TLB_FLUSH + def_bool y + depends on CPU_SUP_AMD + menuconfig PROCESSOR_SELECT bool "Supported processor vendors" if EXPERT help @@ -431,6 +435,7 @@ config CPU_SUP_CYRIX_32 config CPU_SUP_AMD default y bool "Support AMD processors" if PROCESSOR_SELECT + select X86_BROADCAST_TLB_FLUSH help This enables detection, tunings and quirks for AMD processors diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 17b6590748c0..f9b832e971c5 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -338,6 +338,7 @@ #define X86_FEATURE_CLZERO (13*32+ 0) /* "clzero" CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* "irperf" Instructions Retired Count */ #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* "xsaveerptr" Always save/restore FP error pointers */ +#define X86_FEATURE_INVLPGB (13*32+ 3) /* INVLPGB and TLBSYNC instruction supported. */ #define X86_FEATURE_RDPRU (13*32+ 4) /* "rdpru" Read processor register at user level */ #define X86_FEATURE_WBNOINVD (13*32+ 9) /* "wbnoinvd" WBNOINVD instruction */ #define X86_FEATURE_AMD_IBPB (13*32+12) /* Indirect Branch Prediction Barrier */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 02fc2aa06e9e..8fe3b2dda507 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -183,6 +183,13 @@ static inline void cr4_init_shadow(void) extern unsigned long mmu_cr4_features; extern u32 *trampoline_cr4_features; +/* How many pages can we invalidate with one INVLPGB. */ +#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH +extern u16 invlpgb_count_max; +#else +#define invlpgb_count_max 1 +#endif + extern void initialize_tlbstate_and_flush(void); /* diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 79d2e17f6582..bcf73775b4f8 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -29,6 +29,8 @@ #include "cpu.h" +u16 invlpgb_count_max __ro_after_init; + static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) { u32 gprs[8] = { 0 }; @@ -1135,6 +1137,12 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) tlb_lli_2m[ENTRIES] = eax & mask; tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; + + /* Max number of pages INVLPGB can invalidate in one shot */ + if (boot_cpu_has(X86_FEATURE_INVLPGB)) { + cpuid(0x80000008, &eax, &ebx, &ecx, &edx); + invlpgb_count_max = (edx & 0xffff) + 1; + } } static const struct cpu_dev amd_cpu_dev = {