From patchwork Mon Jan 20 02:40:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13944709 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45310C02187 for ; Mon, 20 Jan 2025 02:42:53 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 61C45280005; Sun, 19 Jan 2025 21:42:37 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 5CC56280003; Sun, 19 Jan 2025 21:42:37 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 42C8E280005; Sun, 19 Jan 2025 21:42:37 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0013.hostedemail.com [216.40.44.13]) by kanga.kvack.org (Postfix) with ESMTP id 1EB46280003 for ; Sun, 19 Jan 2025 21:42:37 -0500 (EST) Received: from smtpin02.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay08.hostedemail.com (Postfix) with ESMTP id C38391426F8 for ; Mon, 20 Jan 2025 02:42:36 +0000 (UTC) X-FDA: 83026281912.02.6650B19 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) by imf07.hostedemail.com (Postfix) with ESMTP id 3F64140006 for ; Mon, 20 Jan 2025 02:42:35 +0000 (UTC) Authentication-Results: imf07.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf07.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1737340955; a=rsa-sha256; cv=none; b=DGXGUNGoYGcA6FoK32Rob/RLphzgQtPyblH5JeDvbAauG7PlJlnNv38JKioj4Vufk3VjqN mfcWfSIExDuRsuhIXX3U6LhyzWu+VO6vOHSRPm3g3A5MRhWVQIEkyqYQ3MI7bLUdWR8cLD cDTTAJ6lAeC580Vp4R4nf3s374ty29E= ARC-Authentication-Results: i=1; imf07.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf07.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1737340955; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bH49FN0w3c02qAbIou49rhkotHSjqN3va05zvkVQPxU=; b=OuqhaU/Lf7aaJT/E8C6vxUfPEwwg8hMWBYlqonNJIth1HGsVO2L4ArkB96kRCAlH0ry20L YSZA43NB6kOh5r8PB6FL1fa3Z59DyMudw2dTUbztLI6oU++8U/N1AvZSe/uhbCpJDwDQrX u+BQRoYIlYjHlpPBICjlgk+VCz6D+FE= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tZhis-000000002w5-1WUb; Sun, 19 Jan 2025 21:41:06 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Rik van Riel Subject: [PATCH v6 10/12] x86,tlb: do targeted broadcast flushing from tlbbatch code Date: Sun, 19 Jan 2025 21:40:18 -0500 Message-ID: <20250120024104.1924753-11-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250120024104.1924753-1-riel@surriel.com> References: <20250120024104.1924753-1-riel@surriel.com> MIME-Version: 1.0 X-Rspamd-Server: rspam04 X-Rspamd-Queue-Id: 3F64140006 X-Stat-Signature: 4dg3i9nr7w3oyg7csmiw87uy1w3sqt17 X-Rspam-User: X-HE-Tag: 1737340955-121786 X-HE-Meta: U2FsdGVkX1+nQm4nCW7bnrl5l8SauR2zL1UV2yltIDvvpyacqtyJRhYgHRu73uOPbMpw4s1tMAQlQkp3Z5Pupru9La7/r5fkozS0c4IUQ/rv0VVQAfOcQWJyk4VBWjFxLzosEvvMNEFwhUiKM6O0nr4L+Sld9WFSFR3WnjiEmLQtHyIoueBF9cM7kKL3AUyJv68xfVcm/GL4+h4ZNZ3fX5UF9w6iGUVGno01Zj3FyEXBy/02ZVI5HbHHbXjPh8ZrXtFbGgfsQ+e8D2v0Ud5teFiG97oN+nR6yvMTCHl3v8UPYKY4OTXRc2BXsSP/8HI/chWGevLZU56pR+3PKcMonY0BeHeumwMJowzqCdl3uhYNKDjv9Zq3OehhKHgNbsh0CSUoW+ZdKFSEH4ddKDjEKaGkez1IYggqyMsivSG82vgYtxjOjAo9SjQseEmkA7+Ydmii3m5lZkNpOZF3DF6tAfmIys87R1SZB8i6bnP07oJTMVT0TL1FU6Coe0BW/cipVWRIxkLQaXVj1GWh/w8rFhPQrwkRt82QJzErLDTYPSAo12rGgNDDm4oTEOGdS7MgddYQFDHgRSHN2f277mW0f2xmfDfJ18dDkF68JBnk/0B+ktZZQDiZxDkXiazv03MLGn+JsTTyjFhKjdgi938Cp3iTB477QW3ANR5MBX2fwHXx1bGgbRjLLelKNNPouFK16PDSZX5+mcbMduBDICjH9Laq55c24qMztRgcVzRguuKBPB+DctG5q8ierZQ3zuPmLS0cU3EW8DblbC0erje1XlGcjXuSssB3CNjRMyrLpNrLg1oDlVhLmhJ2ssoswl/wVpUDphwAcS5HFlCSE4jvvYxwaItG0hn9NA9oJ6b4su+SNEgRqJJppR5wOatLESztpZLhcX8FsKgEhiDifgVBdRk3NSiLvZxqhg6Wv5Iho2TulNnSe1DyPWxqdyaE4LbMPExkHRGIbR2Uu34QyqE peFs6jfz r7+RHnsx04kwx/N8OS0M0m4K3Tjv3+EGC//ypr+k9Ty5qmPLGmuGg+a0ycxShFvB8nJgCq8Bb9n69rQsPsfIwicw+oABqGPVqC3AjBvSge6I2oiApmx8sN5ziBQtON4KZHvTEyaLNyvAbfEkjUHUAT/SHMiCoAX7G3YVpeUCL9o0WmEQhd5lzdUWoKEIOhOGRsI5YiZrjuRVoiasdPD2xFkkWy0D59rOJdABhoq3d1bkaG+8pk+QrqkgY5wDJ9+iL1L1tXL4Nudu9y6NVTLVzxiNztbhtlwBVXFgADk0pCD4dMYzVVxbWl0e4seD9MROE+zSQVp+0tL2YBFNyp39ZdpwMyM1+597BrBTiB24CGbccIrgpAbuxgmfW0VDsbv83m8VbKJfwY2idXnhdNu/lxGj4R7ftiUri8NeoZ6NKU24xMsk= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Instead of doing a system-wide TLB flush from arch_tlbbatch_flush, queue up asynchronous, targeted flushes from arch_tlbbatch_add_pending. This also allows us to avoid adding the CPUs of processes using broadcast flushing to the batch->cpumask, and will hopefully further reduce TLB flushing from the reclaim and compaction paths. Signed-off-by: Rik van Riel --- arch/x86/include/asm/tlbbatch.h | 1 + arch/x86/include/asm/tlbflush.h | 12 ++------ arch/x86/mm/tlb.c | 54 +++++++++++++++++++++++++++++++-- 3 files changed, 55 insertions(+), 12 deletions(-) diff --git a/arch/x86/include/asm/tlbbatch.h b/arch/x86/include/asm/tlbbatch.h index 1ad56eb3e8a8..f9a17edf63ad 100644 --- a/arch/x86/include/asm/tlbbatch.h +++ b/arch/x86/include/asm/tlbbatch.h @@ -10,6 +10,7 @@ struct arch_tlbflush_unmap_batch { * the PFNs being flushed.. */ struct cpumask cpumask; + bool used_invlpgb; }; #endif /* _ARCH_X86_TLBBATCH_H */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 5eae5c1aafa5..e5516afdef7d 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -358,21 +358,15 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm) return atomic64_inc_return(&mm->context.tlb_gen); } -static inline void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, - struct mm_struct *mm, - unsigned long uaddr) -{ - inc_mm_tlb_gen(mm); - cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm)); - mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL); -} - static inline void arch_flush_tlb_batched_pending(struct mm_struct *mm) { flush_tlb_mm(mm); } extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch); +extern void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, + struct mm_struct *mm, + unsigned long uaddr); static inline bool pte_flags_need_flush(unsigned long oldflags, unsigned long newflags, diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 08eee1f8573a..f731e6cfaa29 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -1659,9 +1659,7 @@ void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) * a local TLB flush is needed. Optimize this use-case by calling * flush_tlb_func_local() directly in this case. */ - if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) { - invlpgb_flush_all_nonglobals(); - } else if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) { + if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) { flush_tlb_multi(&batch->cpumask, info); } else if (cpumask_test_cpu(cpu, &batch->cpumask)) { lockdep_assert_irqs_enabled(); @@ -1670,12 +1668,62 @@ void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) local_irq_enable(); } + /* + * If we issued (asynchronous) INVLPGB flushes, wait for them here. + * The cpumask above contains only CPUs that were running tasks + * not using broadcast TLB flushing. + */ + if (cpu_feature_enabled(X86_FEATURE_INVLPGB) && batch->used_invlpgb) { + tlbsync(); + migrate_enable(); + batch->used_invlpgb = false; + } + cpumask_clear(&batch->cpumask); put_flush_tlb_info(); put_cpu(); } +void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, + struct mm_struct *mm, + unsigned long uaddr) +{ + if (static_cpu_has(X86_FEATURE_INVLPGB) && mm_global_asid(mm)) { + u16 asid = mm_global_asid(mm); + /* + * Queue up an asynchronous invalidation. The corresponding + * TLBSYNC is done in arch_tlbbatch_flush(), and must be done + * on the same CPU. + */ + if (!batch->used_invlpgb) { + batch->used_invlpgb = true; + migrate_disable(); + } + invlpgb_flush_user_nr_nosync(kern_pcid(asid), uaddr, 1, false); + /* Do any CPUs supporting INVLPGB need PTI? */ + if (static_cpu_has(X86_FEATURE_PTI)) + invlpgb_flush_user_nr_nosync(user_pcid(asid), uaddr, 1, false); + + /* + * Some CPUs might still be using a local ASID for this + * process, and require IPIs, while others are using the + * global ASID. + * + * In this corner case we need to do both the broadcast + * TLB invalidation, and send IPIs. The IPIs will help + * stragglers transition to the broadcast ASID. + */ + if (READ_ONCE(mm->context.asid_transition)) + goto also_send_ipi; + } else { +also_send_ipi: + inc_mm_tlb_gen(mm); + cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm)); + } + mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL); +} + /* * Blindly accessing user memory from NMI context can be dangerous * if we're in the middle of switching the current user task or