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b=Dd37oMsPtbW4ALKanGSu4JlamSbkCS+V1cxIvuo17CWneEgDv8P5Irm6dPf5q6vIikPAXN ClGGXuywu4Fco0PV92nXUMVV7/pKCO/UVCvJP3L1T2CM+LUOXWbg6IHQ43swJyBTsDiMMc R9JtsWNcEvsTWwmId90jrvMuu5UIok4= ARC-Authentication-Results: i=1; imf01.hostedemail.com; dkim=none; spf=pass (imf01.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com; dmarc=none ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1737340949; a=rsa-sha256; cv=none; b=yVB5Wo/NeFXaxcWPqZwQI6mTvbsE87gFYp3OhCjO7oho+uoNLNvMPuxFMWW7ugffZzFfRL Cxe56sqaDO6B7kQJq8y+jhofP2Kx8pCjtm5EN63eeePBBFKdabZe+AcEEn4JJszm7POxXI sirXzz9yGG2xqv8KAeGCpz7iH+e3Gfk= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tZhis-000000002w5-0wWs; Sun, 19 Jan 2025 21:41:06 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Rik van Riel Subject: [PATCH v6 04/12] x86/mm: get INVLPGB count max from CPUID Date: Sun, 19 Jan 2025 21:40:12 -0500 Message-ID: <20250120024104.1924753-5-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250120024104.1924753-1-riel@surriel.com> References: <20250120024104.1924753-1-riel@surriel.com> MIME-Version: 1.0 X-Rspamd-Server: rspam02 X-Rspamd-Queue-Id: 08D4B40006 X-Stat-Signature: ckt8x631edtpw9ugradto6a45p7igw7m X-Rspam-User: X-HE-Tag: 1737340948-810835 X-HE-Meta: U2FsdGVkX1/szOldOeGYexpjExOqdkPj9Jtcyp2UQntb8WoS+DC7LOJPBLAUQ0tyL8ipKbIF1rgTejXZMGZ4C5r9oMFgH0pVIhGHC7KKe4CiO8yWYPF/0jQ6WUJ2kf0NIu702mzzPkG+0DjSbjD10iBRW59rBvTXWNIPtzDyABbZpOT2ofDP1xfJ+jSypM/qUwoU5DdCXkFkXlwptSlZ/kpG1MF3jC8RfVAobE5VqBMxIVYDXOhfbQ6e3w/pZ9kuk9S3cc/ZF+eaP/D1KCwFEYneU7aab5jwJrjx1xLX2FMJPsa0Crwiw/VxjLCIdQc7lF0jV6GP0cdD1U6aU6Cn9o0G5DvfJgX+I9nTGb1kHzX6iGbWNoNKrSYyUuHZi6mJYNZG0uPH+19wtK3LEdyeJP8LzIurzVWR5DlITZyo6Neh9MVI4JFN+2RcQWdz589UDiwdqe4p7PUOOCtc9//Zr/XTt6HqTsyxEk4+KZyGKU8VrSTeOicTEOqcvITQBbnbDGKT3buMWzNJMM+P+SZ5tUMo6b9ggzzo2pspoSFWLuBi+AHAAD3XzUGW2DXg9r7ml0RAFmeFxsvWhCwD4YVh5vz6QP3fltSdhNuoJO2zanA2dqt1FzQ6Q1BUEjt/Wk3S+f4KbCEJPWAIvvVbq162KN+vxJpRudCfEvYY40XUP7AmIBeffCbo/vxBaQy8kiAqMOuWjNrWuS/H7TSSGKSvWOdRWfFO5Td8hTaPdAepwsct8DzZVb0+4+uhivw+efgNdDKv/ukTNTQ8qUs/vxbQ7i5f50dBtofgYpwwOlEs80qCTlxXP9Iw7w05yScNdzDhoo0lJsi50Ks41gimXW9hEp53N/JNaNRW6df6iNDmPM0zO1W7vOBkwFGGKjAxl6aupKhlRDOQkMitR6EeqXGy+caOBg7iQKmBB4l97M5Da5jSjVKD5WP4UbxQlyhiEVgK0RMbj2rgFyn2xiQRHHF Lh7GsOT6 Dqm3qzZIDHkAC0owQ8dfikintDEAyOBtNFb8HEvJGiVx1HXdHkQIF0xmKa2Nm7LX0a8gI0rosv80fVRU0uCrD8u25psiDS6sAVczXU6f62ALfPFLbGMyLU5vDh838puX5Gn1DagIZR62eZ+/cCW/ZiH/ZSfbqzh7nM+ngZT6k+7H+b3UqTZWXC6VafEzGuOlp1FmaBmFI2MuYnTxeigtT6iMkpm/FqpdLIl72BhGmC2I7QbStUfgJVg0SAhLhD6c5lSqj8n0S5d2rPmhDLgmcoDJiFSKywe9/B1cO8jPU8Xfd3y5Y/cPVFHeTihxU88EAXttd77j061KdUEO77SN96X01Q5WjnIzqqSb8X3B8afdu8YMnQVEw369Hs8Ss9N6E2F8Y X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: The CPU advertises the maximum number of pages that can be shot down with one INVLPGB instruction in the CPUID data. Save that information for later use. Signed-off-by: Rik van Riel --- arch/x86/Kconfig.cpu | 5 +++++ arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/tlbflush.h | 7 +++++++ arch/x86/kernel/cpu/amd.c | 8 ++++++++ 4 files changed, 21 insertions(+) diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 2a7279d80460..abe013a1b076 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -395,6 +395,10 @@ config X86_VMX_FEATURE_NAMES def_bool y depends on IA32_FEAT_CTL +config X86_BROADCAST_TLB_FLUSH + def_bool y + depends on CPU_SUP_AMD && 64BIT + menuconfig PROCESSOR_SELECT bool "Supported processor vendors" if EXPERT help @@ -431,6 +435,7 @@ config CPU_SUP_CYRIX_32 config CPU_SUP_AMD default y bool "Support AMD processors" if PROCESSOR_SELECT + select X86_BROADCAST_TLB_FLUSH help This enables detection, tunings and quirks for AMD processors diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 17b6590748c0..f9b832e971c5 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -338,6 +338,7 @@ #define X86_FEATURE_CLZERO (13*32+ 0) /* "clzero" CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* "irperf" Instructions Retired Count */ #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* "xsaveerptr" Always save/restore FP error pointers */ +#define X86_FEATURE_INVLPGB (13*32+ 3) /* INVLPGB and TLBSYNC instruction supported. */ #define X86_FEATURE_RDPRU (13*32+ 4) /* "rdpru" Read processor register at user level */ #define X86_FEATURE_WBNOINVD (13*32+ 9) /* "wbnoinvd" WBNOINVD instruction */ #define X86_FEATURE_AMD_IBPB (13*32+12) /* Indirect Branch Prediction Barrier */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 02fc2aa06e9e..8fe3b2dda507 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -183,6 +183,13 @@ static inline void cr4_init_shadow(void) extern unsigned long mmu_cr4_features; extern u32 *trampoline_cr4_features; +/* How many pages can we invalidate with one INVLPGB. */ +#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH +extern u16 invlpgb_count_max; +#else +#define invlpgb_count_max 1 +#endif + extern void initialize_tlbstate_and_flush(void); /* diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 79d2e17f6582..bcf73775b4f8 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -29,6 +29,8 @@ #include "cpu.h" +u16 invlpgb_count_max __ro_after_init; + static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) { u32 gprs[8] = { 0 }; @@ -1135,6 +1137,12 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) tlb_lli_2m[ENTRIES] = eax & mask; tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; + + /* Max number of pages INVLPGB can invalidate in one shot */ + if (boot_cpu_has(X86_FEATURE_INVLPGB)) { + cpuid(0x80000008, &eax, &ebx, &ecx, &edx); + invlpgb_count_max = (edx & 0xffff) + 1; + } } static const struct cpu_dev amd_cpu_dev = {