From patchwork Mon Jan 20 02:40:13 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13944702 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B373C0218A for ; Mon, 20 Jan 2025 02:42:37 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id A2301280002; Sun, 19 Jan 2025 21:42:30 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 7384A6B008C; Sun, 19 Jan 2025 21:42:30 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 3A81D6B0099; Sun, 19 Jan 2025 21:42:30 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0012.hostedemail.com [216.40.44.12]) by kanga.kvack.org (Postfix) with ESMTP id E09206B008C for ; Sun, 19 Jan 2025 21:42:29 -0500 (EST) Received: from smtpin14.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay03.hostedemail.com (Postfix) with ESMTP id 99754A25C4 for ; Mon, 20 Jan 2025 02:42:29 +0000 (UTC) X-FDA: 83026281618.14.93EE4FA Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) by imf03.hostedemail.com (Postfix) with ESMTP id 17AD820004 for ; Mon, 20 Jan 2025 02:42:27 +0000 (UTC) Authentication-Results: imf03.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf03.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1737340948; a=rsa-sha256; cv=none; b=FEjnpKbiyGVvAc6x3NLn/4y4hXJjsWTnlDPLYnouo7iStaYoOeljm53cU7Usdb/Ciq4GCG Ms4NKTbo6X7tVB0Iw9ioGlWngN7gZzr1CLbPmcfUABtlzTKeVxeVWEf770T3i6EjAhbvzj IxKNY9znfTK1MLvocXesbw7ZDLhjCaU= ARC-Authentication-Results: i=1; imf03.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf03.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1737340948; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1K8kB1I4+9t9TIYqSgJN8D2rNOhCjXKJjmT94NTU88I=; b=e77uxrbbAGlwRKN7TOfGOyAbBGxw8oH5Yt7cjkg1Q81zaOa6HfFlpS/3lLwB8xm81Ey/nT 1cHyamRYTlDj4eT2r10bjQuLC3sjMZv95KY6+9H4V20uGSWsIPQvSmOXEuBCxXyfulfdtO febzdgC57Y/xVwCd66iH9fOai+QANkQ= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tZhis-000000002w5-11sM; Sun, 19 Jan 2025 21:41:06 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Rik van Riel Subject: [PATCH v6 05/12] x86/mm: add INVLPGB support code Date: Sun, 19 Jan 2025 21:40:13 -0500 Message-ID: <20250120024104.1924753-6-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250120024104.1924753-1-riel@surriel.com> References: <20250120024104.1924753-1-riel@surriel.com> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Queue-Id: 17AD820004 X-Rspamd-Server: rspam10 X-Stat-Signature: 4u7crojmfqcgxtn8xjxchnb7is1hmpam X-HE-Tag: 1737340947-217789 X-HE-Meta: U2FsdGVkX19WTmpPB5u1apvF/Ql+I7UPbPGkevWEG3TX/mUZoZ6jAX/Jmxi4WHZe/SDiR1PMSzv0jhHpboRCeDtproN48uWqAID2owl2+L4cMF/U/lalVxklLfoZinarIICrhFkJxfMMAtjPIXbEI9M/OxDYwZoK38+QqJP6ZxN08dR7jp/ovzUEfq9IOmvXYaMqzvJWKo1JWj4ShTxAcfw0FG8NIGgxZcZ9k2pExwTm+6P9LBwI2+fNJOrg1+nNkQyLHVeiZL3mpFzfoXx+4/3/rNJeDtifOIHI39WPhJE24XoMnxAuFJnAN6uTPiWyvwrP0JSudIp2L/PpOI4ofIUixwrEmNl/gKguNz8yZPblnNYf9RC+cPqwbAgfbFxj9M/rLgKMr+c4pjH0r/6bvtva2qDExLC6E8cXemsMMeSRDIPujwaJgyxm7cVas+YZh1HNSonchmPCES1k79BZYFz/RpiGp4LIkN9y4gKRpdOXJws0MpRGvtvkKkgwwV7Ix4Rsq8dac94vhKDQY8YCuQOzIPuxfzSSM5+3BOUIPKTLbw8d/+J20flWRNCNnw9fNJve31weP4dXhjkt9tJI/1H4hFPdkVwfYuVpy7nabYjRQIzo6AXLrhfBlkWfJGfHfsa5GRydUmIC5B559tw31nPTxhK33w3tflMmSOtBKVOR4+bNZ9gvQC5oUxoXi7acKoMNNQNzgvR3LrBAn15jnD3TkQnaGfVF+7gmZZV8nwBSZM60qgaY/BMufsG9FdJZR9vWOjYJmAvhBmPsulhA61jQSd8Ovbi9KmiBIWQgExZjMg9GLuXbluE3v15decBMkV3b9eF52rPyCO6/JYjCcu0FuFtsi8RzIQH3i/2qcmX9rNmUAk3z3kVtSPxVfRpTrsPx83UNaCrBZEFih3FvdXfmDLdlpDuBm7sMN/MtyLzkbNVNvY6E6z6KY9DtMggBu5e9v57Buix17kCa1tr pv2luZMZ lwg3S+Ct4PZ9vX2DBLA1/x/WJPmT7QH9skrnYf79JmC4FLOMikI8Y8Jimk/rIjQyCA9gy9OgNNII1Bkx1B0N+5deDG49LwkHFus4xk+cLoa49sUtHN2gVS3vdIMcyEOD7WyGrBKJGNM8T2vt97zqTVi7GfQNAkq+Kj7ehKSfbIY2xuIckWHVm/49JZD05dxajjfUfIeU0bci3hUbElObOIM5fkxj5JW1dsvY2LzQxlsEp+r2qD3uF7w9yRILoHQjwZy/j1K9C1mpKpQtKB2usn80n4/sc2wvncYmUwRzW0qUWWyWKXB6ePksmV1iuQXY8wA7S/76pVlfAZ2gcRe63GCjE8wz3nhwW75DZMkxqqFzzbZCAeWUZ+1HtOfDv8edvyHBis48qnjdz0SY= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Add invlpgb.h with the helper functions and definitions needed to use broadcast TLB invalidation on AMD EPYC 3 and newer CPUs. Signed-off-by: Rik van Riel --- arch/x86/include/asm/invlpgb.h | 97 +++++++++++++++++++++++++++++++++ arch/x86/include/asm/tlbflush.h | 1 + 2 files changed, 98 insertions(+) create mode 100644 arch/x86/include/asm/invlpgb.h diff --git a/arch/x86/include/asm/invlpgb.h b/arch/x86/include/asm/invlpgb.h new file mode 100644 index 000000000000..4dfd09e65fa6 --- /dev/null +++ b/arch/x86/include/asm/invlpgb.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_INVLPGB +#define _ASM_X86_INVLPGB + +#include +#include + +/* + * INVLPGB does broadcast TLB invalidation across all the CPUs in the system. + * + * The INVLPGB instruction is weakly ordered, and a batch of invalidations can + * be done in a parallel fashion. + * + * TLBSYNC is used to ensure that pending INVLPGB invalidations initiated from + * this CPU have completed. + */ +static inline void __invlpgb(unsigned long asid, unsigned long pcid, + unsigned long addr, u16 extra_count, + bool pmd_stride, unsigned long flags) +{ + u32 edx = (pcid << 16) | asid; + u32 ecx = (pmd_stride << 31) | extra_count; + u64 rax = addr | flags; + + /* INVLPGB; supported in binutils >= 2.36. */ + asm volatile(".byte 0x0f, 0x01, 0xfe" : : "a" (rax), "c" (ecx), "d" (edx)); +} + +/* Wait for INVLPGB originated by this CPU to complete. */ +static inline void tlbsync(void) +{ + cant_migrate(); + /* TLBSYNC: supported in binutils >= 0.36. */ + asm volatile(".byte 0x0f, 0x01, 0xff" ::: "memory"); +} + +/* + * INVLPGB can be targeted by virtual address, PCID, ASID, or any combination + * of the three. For example: + * - INVLPGB_VA | INVLPGB_INCLUDE_GLOBAL: invalidate all TLB entries at the address + * - INVLPGB_PCID: invalidate all TLB entries matching the PCID + * + * The first can be used to invalidate (kernel) mappings at a particular + * address across all processes. + * + * The latter invalidates all TLB entries matching a PCID. + */ +#define INVLPGB_VA BIT(0) +#define INVLPGB_PCID BIT(1) +#define INVLPGB_ASID BIT(2) +#define INVLPGB_INCLUDE_GLOBAL BIT(3) +#define INVLPGB_FINAL_ONLY BIT(4) +#define INVLPGB_INCLUDE_NESTED BIT(5) + +/* Flush all mappings for a given pcid and addr, not including globals. */ +static inline void invlpgb_flush_user(unsigned long pcid, + unsigned long addr) +{ + __invlpgb(0, pcid, addr, 0, 0, INVLPGB_PCID | INVLPGB_VA); + tlbsync(); +} + +static inline void invlpgb_flush_user_nr_nosync(unsigned long pcid, + unsigned long addr, + u16 nr, + bool pmd_stride) +{ + __invlpgb(0, pcid, addr, nr - 1, pmd_stride, INVLPGB_PCID | INVLPGB_VA); +} + +/* Flush all mappings for a given PCID, not including globals. */ +static inline void invlpgb_flush_single_pcid_nosync(unsigned long pcid) +{ + __invlpgb(0, pcid, 0, 0, 0, INVLPGB_PCID); +} + +/* Flush all mappings, including globals, for all PCIDs. */ +static inline void invlpgb_flush_all(void) +{ + __invlpgb(0, 0, 0, 0, 0, INVLPGB_INCLUDE_GLOBAL); + tlbsync(); +} + +/* Flush addr, including globals, for all PCIDs. */ +static inline void invlpgb_flush_addr_nosync(unsigned long addr, u16 nr) +{ + __invlpgb(0, 0, addr, nr - 1, 0, INVLPGB_INCLUDE_GLOBAL); +} + +/* Flush all mappings for all PCIDs except globals. */ +static inline void invlpgb_flush_all_nonglobals(void) +{ + __invlpgb(0, 0, 0, 0, 0, 0); + tlbsync(); +} + +#endif /* _ASM_X86_INVLPGB */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 8fe3b2dda507..dba5caa4a9f4 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include