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b=vZs7q2uOhTQXNM1+Stbtxahfgo5ZZ/fwCZQBe4FwxjDJy09t9I68Eu5qGGSceP9rNC7zQO wLkTrkxE4NqcETatzwjBN1RJGpFbA8d5zDRSAVVOkFXYfMJ23RAdhKzKU6qma/dcVjlXYV Mf6QsP9lHUb/gdeNHP1Z5QTcAlXdeYw= ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1737606570; a=rsa-sha256; cv=none; b=axneOkb0Wuv95lKJ9MVYku7lonEHETmqIxiFGxZBk5pD7ymMFVhU6eByYGRBtJcMaIVii6 5tYYaLFvH+WQe6ErrU5ira5LkPr3pGHDzqUiaoPPF63YpiMOvfGUHmTm+4Uus6Nwn0MSIo Hac+NcY4UCrmVMiGK0Xljv0o6rosHDs= ARC-Authentication-Results: i=1; imf25.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf25.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1taols-000000005uH-3NEp; Wed, 22 Jan 2025 23:24:48 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Rik van Riel Subject: [PATCH v7 10/12] x86/mm: do targeted broadcast flushing from tlbbatch code Date: Wed, 22 Jan 2025 23:23:29 -0500 Message-ID: <20250123042447.2259648-11-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250123042447.2259648-1-riel@surriel.com> References: <20250123042447.2259648-1-riel@surriel.com> MIME-Version: 1.0 X-Rspamd-Queue-Id: C2A4EA0002 X-Stat-Signature: 5zfhhitkbda68f7845rn169gno5xepnb X-Rspam-User: X-Rspamd-Server: rspam12 X-HE-Tag: 1737606570-253561 X-HE-Meta: U2FsdGVkX1909B3B2cgloNq/edB1KnwjNWPbos8suqjiuwOcPNKMU2oQUBcWdv+CyPmsRrKxRK121SBUoeXP+ZV5n7Qat35T5KAwqJHednlrJyxIGQjsBc8mz1Q86UdmrRdPv6ZQ5/7AoTHWJfq0zg7PVmCwrGHtXY5a25KGNBsoL7vINZ23EJouM+kHwhrEUwqNoxpL6Ihq0sN6nIs5lPIU2iASfuyhS+BkATR1rxffRdTP5gtDF6s9FSa8NyNOa28x48Rq4Q3zqrFymOYmHM0XBTYFM5RWPsy2jqLBfE27ZbFAt4i0DsMo7l3UKByPTLYDyhtjKVrOFKrQojCAv+q4/Jx2X+XvNihZYmuAmHlPlgqub6hGrRXFLFBxPUZII0bHUsSfLrYn+d0LDlV9XRmyctht9OpSC4lnyN310ngxgSn6TMk+56Y2wgpUHdmAOVMQ9BP3VmfsgUQw0UpX1QyoWT5p9vqWMg40QEIDjLXoLHqujHVh41QLabws9dnkFSGfCQR3T9+PSgX2KCeIVM/JpEKOMSyVsAnmKCwO+CxSwp04SdiMLMcZCb8mKfzjVhjW4pERi+LumT2BeiyXASKgbZ4wGH976MyECnh9RjwYXTnXhMU4SKUrFeJev+0ca4mRzwBjhHSJsz1YnJmj62q9+cEPGzYjd3ocXuBLN6RZ2tSw8vUC/J0f73xKQ21YJMsKvJhJ3JOc4R35jZMikWlPFnK/zz9SSoGZTuycEw/8hfM1dJm4GthJz77zca5Ae2xaK7rE6K/pKrmwJ24FOlQmL7F3skDqDm0vWACE8D6a2MDnIHG67z4s66Gp8vMnTr7WFzTsjvzkNnjGcRE4XxEa76ylVmR2Nj/1wk2/+fBviXZ5/zu/fC12fiAnbysj7AVhaQjnlBi/gOroXkZ65PXcxMe3+i3qvxM89sdoDwoKZai6qXceZ1w5d6ZSlLvBTRKrqyb22mv4PwZfBj+ wxzu5vkx uP3u3WuCX+sUXo01Zlk8aF70xrsVws3KIbeETkEHH1ZOSZPIEJ6hrvQy0ngT+jRiCt91VARgvFbahCe3oBacWoYQl+jNKR498XPNjSguqvbIfgrfrdB4N184N5aHnurTvG776NCkx5dBPp9BXwq20qCQQu/2FpXPTYgJGFT5/rSJ8uLeitdtCvDzhxiQ8EpA3gAM/zB9a7+DhcYeIYj/TXtkRxq176rSBNcg7/BwRr7TRWsCosQeMwDn7VdnXlGX8zoys3q8WsoGErwh/ynQyEhEs5VbfkmJ1B00BlseI73XTh8h29nParHkq4W09mW+OCJr6MPuaosq7W9+/Wo23wvQmlqORInDfPhHLuuXe/DcE+35JrkLptqHJ+iDYvMYjGoLIAqlivRSfLIp2n/ImH/cztec9FH1sk6V1P0axakulsTc= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Instead of doing a system-wide TLB flush from arch_tlbbatch_flush, queue up asynchronous, targeted flushes from arch_tlbbatch_add_pending. This also allows us to avoid adding the CPUs of processes using broadcast flushing to the batch->cpumask, and will hopefully further reduce TLB flushing from the reclaim and compaction paths. Signed-off-by: Rik van Riel --- arch/x86/include/asm/tlbbatch.h | 1 + arch/x86/include/asm/tlbflush.h | 12 ++----- arch/x86/mm/tlb.c | 57 +++++++++++++++++++++++++++++++-- 3 files changed, 58 insertions(+), 12 deletions(-) diff --git a/arch/x86/include/asm/tlbbatch.h b/arch/x86/include/asm/tlbbatch.h index 1ad56eb3e8a8..f9a17edf63ad 100644 --- a/arch/x86/include/asm/tlbbatch.h +++ b/arch/x86/include/asm/tlbbatch.h @@ -10,6 +10,7 @@ struct arch_tlbflush_unmap_batch { * the PFNs being flushed.. */ struct cpumask cpumask; + bool used_invlpgb; }; #endif /* _ARCH_X86_TLBBATCH_H */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 7e2f3f7f6455..f8aaa4bcb4d8 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -359,21 +359,15 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm) return atomic64_inc_return(&mm->context.tlb_gen); } -static inline void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, - struct mm_struct *mm, - unsigned long uaddr) -{ - inc_mm_tlb_gen(mm); - cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm)); - mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL); -} - static inline void arch_flush_tlb_batched_pending(struct mm_struct *mm) { flush_tlb_mm(mm); } extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch); +extern void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, + struct mm_struct *mm, + unsigned long uaddr); static inline bool pte_flags_need_flush(unsigned long oldflags, unsigned long newflags, diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index b55361fabb89..9fee2aff8153 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -1641,9 +1641,7 @@ void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) * a local TLB flush is needed. Optimize this use-case by calling * flush_tlb_func_local() directly in this case. */ - if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) { - invlpgb_flush_all_nonglobals(); - } else if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) { + if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) { flush_tlb_multi(&batch->cpumask, info); } else if (cpumask_test_cpu(cpu, &batch->cpumask)) { lockdep_assert_irqs_enabled(); @@ -1652,12 +1650,65 @@ void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) local_irq_enable(); } + /* + * If we issued (asynchronous) INVLPGB flushes, wait for them here. + * The cpumask above contains only CPUs that were running tasks + * not using broadcast TLB flushing. + */ + if (cpu_feature_enabled(X86_FEATURE_INVLPGB) && batch->used_invlpgb) { + tlbsync(); + migrate_enable(); + batch->used_invlpgb = false; + } + cpumask_clear(&batch->cpumask); put_flush_tlb_info(); put_cpu(); } +void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, + struct mm_struct *mm, + unsigned long uaddr) +{ + u16 asid = mm_global_asid(mm); + + if (asid) { + /* + * Queue up an asynchronous invalidation. The corresponding + * TLBSYNC is done in arch_tlbbatch_flush(), and must be done + * on the same CPU. + */ + if (!batch->used_invlpgb) { + batch->used_invlpgb = true; + migrate_disable(); + } + invlpgb_flush_user_nr_nosync(kern_pcid(asid), uaddr, 1, false); + /* Do any CPUs supporting INVLPGB need PTI? */ + if (static_cpu_has(X86_FEATURE_PTI)) + invlpgb_flush_user_nr_nosync(user_pcid(asid), uaddr, 1, false); + + /* + * Some CPUs might still be using a local ASID for this + * process, and require IPIs, while others are using the + * global ASID. + * + * In this corner case we need to do both the broadcast + * TLB invalidation, and send IPIs. The IPIs will help + * stragglers transition to the broadcast ASID. + */ + if (READ_ONCE(mm->context.asid_transition)) + asid = 0; + } + + if (!asid) { + inc_mm_tlb_gen(mm); + cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm)); + } + + mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL); +} + /* * Blindly accessing user memory from NMI context can be dangerous * if we're in the middle of switching the current user task or