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b=f4zxfXNVdyLiumGHP5kdHgfhp/dNJC5+NoEm7rVLgB0e2mAZsmPEL0ENHkK+QGJ31CRhm3 vE/mP5IaEl3jno9XOD4CTotLESCfVm9AnK+LT9JKjTv126mzTOYn7cwUVwYMX2gdIvQ/uF dxLZ46jSp9OdmhJbSy3UynUL2esHxpk= ARC-Authentication-Results: i=1; imf20.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf20.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1737606627; a=rsa-sha256; cv=none; b=YnPZ6t/0ffh2SFpRKrGXkHltXh+LUkKV/eIXvBvkUqzRcBnyIACzHrjprF+ZVbj1FAIGWs +j9zJFjUxT+9CWwSnbMXCd+WafAWlqSlXQ2/B+Dja6y5DO2sloVFab0bTC1mJ+99uPUooT /c7NGR9CVFdMniWCRZcz860brg6baHc= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1taols-000000005uH-2kyx; Wed, 22 Jan 2025 23:24:48 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Rik van Riel Subject: [PATCH v7 04/12] x86/mm: get INVLPGB count max from CPUID Date: Wed, 22 Jan 2025 23:23:23 -0500 Message-ID: <20250123042447.2259648-5-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250123042447.2259648-1-riel@surriel.com> References: <20250123042447.2259648-1-riel@surriel.com> MIME-Version: 1.0 X-Rspamd-Queue-Id: 6C7A61C0006 X-Stat-Signature: 7q6atiuzb716w1pe4q8uk9i6emgo8957 X-Rspamd-Server: rspam08 X-Rspam-User: X-HE-Tag: 1737606627-79670 X-HE-Meta: U2FsdGVkX191YWbKLjZpyOltf9xSBL/o51ZqATt+stzg7+j2wa+8LvkYFeC2xyoe42VaXCOCXiPYrzC+7VPRMVUpcshNY7j1Ww86Iid0KAbCfgFcMz0ngESUbu1aCx72jttjQfKFTpOR3tQx2r6CH+LEX9ybyTRL+96aaiDWTZZ0iANDCRH4g4I1vtK7kSWu57V2EYuKMft+5ZcOPWl5Rosk4uNBN63FvgM0e4kutEZqYm33WvNDPHYe6DXmBpebJL3UnwgvPxO43jU2/nim7P7xHpvHIFRavXZKNsfzOxnOTOWGxTy1ZeN+oH4xvIKarfd8PZEv/Ob88/yPhJDvyhDIZffV7023FENze/eA+qH5tD8zPZfxLcrpljQzgsWjr4VWHtG1Li2DiJU8xnRp2dxqBJEiyuA8uuePDKcIazkeAZoWWrRLftisDzS5eGdeueZ2C19/feCTRjCbNOg8Db4NToaFLXX6scYQqoRiXlaLV+rmudAAwR4XxyLzkfd+GF5xSSlzbo1htMxDXGBrjl0/o+QRtmeVHM3fZmfeKH44f2lz0R2i6swX6XdU5tP2hw9I8Q5jgiR7dBS9Bl6JwhTkoHLTuBqK8bbMoFwzxiT2ausUBla8WimB5e6iI6Lnqy49cTogsqG8lijthoWSh/RD8lpSFAHSgcZPc397HdwXA5S3CTyRzz+MPYNhxfwelIEXKBDCp91JIiaUooLCG16Hpf8QEog/jgX/ZG5qyVfmlqUhVjwBt2HUUyRrVbG6HXJw8/BfdgPkDMROWIt6L9L5BF9KlVevyWJ8OPnlpKN94VEWcuP+Y9IdKb/MqipwThqBJ1T2wJPlZvjapwtucLMD3hZ+6Cst18ocmYG2ExNbNg5zfc6QPTOKTWxdBfdMjmlr9/pKDgybsMI2ntSS7fUBOux2nXgFRRiXM3gsQrFR+K147jbGD5d3oP53/pv00R2awCEuMLvHz4L+rlX /lSFFGcy FxbW4sFVGZl6sifaYPNvk7zQKP7091OPkMLlfihm8nwJxScFxXkGpWstq0l6sHIVVQ8GXyAX4fqAHW7hX1gS8NVruI+1DUPA9SiyK2IrIxIcc1fvvg46WwON6dW4DAirLM9a5DPNxY3Ati6HgGVZj047R8ovuOLRKCIV2wVV0rlJ91p/SuM677DXGxj6kxAkpndMRcr2rQmrFQzAG8PNC22utUwXZP3yyU7GbTzqxxMhOEJXz07fCYZlWyGoI1/J6dO9Sbj+svwKiB9m6z9scT2hPDQfjjB+PegZtmw2XkFfaxbmaRxIZK2bUZQ6dfhxgOoltnewedvsnzrTSa9tsRbYpUJq4nlR3lxekdSLSo4giEKVCj3NWwpMKVcVma64UQ1EE X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: The CPU advertises the maximum number of pages that can be shot down with one INVLPGB instruction in the CPUID data. Save that information for later use. Signed-off-by: Rik van Riel --- arch/x86/Kconfig.cpu | 5 +++++ arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/tlbflush.h | 7 +++++++ arch/x86/kernel/cpu/amd.c | 8 ++++++++ 4 files changed, 21 insertions(+) diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 2a7279d80460..abe013a1b076 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -395,6 +395,10 @@ config X86_VMX_FEATURE_NAMES def_bool y depends on IA32_FEAT_CTL +config X86_BROADCAST_TLB_FLUSH + def_bool y + depends on CPU_SUP_AMD && 64BIT + menuconfig PROCESSOR_SELECT bool "Supported processor vendors" if EXPERT help @@ -431,6 +435,7 @@ config CPU_SUP_CYRIX_32 config CPU_SUP_AMD default y bool "Support AMD processors" if PROCESSOR_SELECT + select X86_BROADCAST_TLB_FLUSH help This enables detection, tunings and quirks for AMD processors diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 17b6590748c0..f9b832e971c5 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -338,6 +338,7 @@ #define X86_FEATURE_CLZERO (13*32+ 0) /* "clzero" CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* "irperf" Instructions Retired Count */ #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* "xsaveerptr" Always save/restore FP error pointers */ +#define X86_FEATURE_INVLPGB (13*32+ 3) /* INVLPGB and TLBSYNC instruction supported. */ #define X86_FEATURE_RDPRU (13*32+ 4) /* "rdpru" Read processor register at user level */ #define X86_FEATURE_WBNOINVD (13*32+ 9) /* "wbnoinvd" WBNOINVD instruction */ #define X86_FEATURE_AMD_IBPB (13*32+12) /* Indirect Branch Prediction Barrier */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 02fc2aa06e9e..8fe3b2dda507 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -183,6 +183,13 @@ static inline void cr4_init_shadow(void) extern unsigned long mmu_cr4_features; extern u32 *trampoline_cr4_features; +/* How many pages can we invalidate with one INVLPGB. */ +#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH +extern u16 invlpgb_count_max; +#else +#define invlpgb_count_max 1 +#endif + extern void initialize_tlbstate_and_flush(void); /* diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 79d2e17f6582..bcf73775b4f8 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -29,6 +29,8 @@ #include "cpu.h" +u16 invlpgb_count_max __ro_after_init; + static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) { u32 gprs[8] = { 0 }; @@ -1135,6 +1137,12 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) tlb_lli_2m[ENTRIES] = eax & mask; tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; + + /* Max number of pages INVLPGB can invalidate in one shot */ + if (boot_cpu_has(X86_FEATURE_INVLPGB)) { + cpuid(0x80000008, &eax, &ebx, &ecx, &edx); + invlpgb_count_max = (edx & 0xffff) + 1; + } } static const struct cpu_dev amd_cpu_dev = {