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Tue, 04 Feb 2025 17:22:27 -0800 (PST) From: Deepak Gupta Date: Tue, 04 Feb 2025 17:22:05 -0800 Subject: [PATCH v9 18/26] riscv/ptrace: riscv cfi status and state via ptrace and in core files MIME-Version: 1.0 Message-Id: <20250204-v5_user_cfi_series-v9-18-b37a49c5205c@rivosinc.com> References: <20250204-v5_user_cfi_series-v9-0-b37a49c5205c@rivosinc.com> In-Reply-To: <20250204-v5_user_cfi_series-v9-0-b37a49c5205c@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta X-Mailer: b4 0.14.0 X-Stat-Signature: dbc7wxp78k38hraxtw57q1hr5e7m5jkn X-Rspam-User: X-Rspamd-Queue-Id: 86DD51C0007 X-Rspamd-Server: rspam03 X-HE-Tag: 1738718549-289643 X-HE-Meta: U2FsdGVkX19zK+pAJ1twwzx7q3drLHo2+uOvh6Afud+KVamSiiec1djl8qQs58Uhjy8l1R/Bzy1/6Xtq+oxS7LxJDKX96bN7Q/XC5U5V7QJUagYdBQ3/GH1wZzCqiLq8tl0Q3iEVoo+nfftZgPXL2melh2pfyLzf2IGIzF6X+/VeZSc+WZL8dck/sT/4xpU8UrhvKw6hFTKilhy7r/NrN/VFG1HdA1ijw+501+8BLEYQXJhZHE2IrWN9sJoYPkJrkISfrtCN5vWlHCb9GL06OibkPUYn7y2bu2mBjNVDc3BNORW4CeI3QeZ1QiI6taiPfV2u54HLmNgPEoK9bnM8b0vW7cYBQcB6I92k7LP6l5OKBaPX5vdu7ymdde9YkGsz2ajuEaG82tL1B/fTRbbXzDgblai4BexJvioCaHd3qtXbhyXPJ6FqWp26Yj7VoomJ5pkBZb+B01PaTtsi7EJ+s+hIrXS15JwAAbB974wHY6DT8EhW4DRY/47MtHUUulzjUOCc5rf0TsXoDnMx7NnXsUmRmWF8IluCqoTmqq4i5bu4xQKNhFe1ptll9pObQ8i6O3iwYutCJdjlLuVbQgYQ69xa9Q7BFq9DD0OCHQim8KG5wL5oIzUeI5I4c52oNK+ckSfBWfUZUNHRSiW+OdhWXlgLPh0BUKGfIDxegmOym4VSm5K4GzyozsilUHJPip92Bz9njMREiciTyt+Yj90LA/NLTKfTdN4B0dJAeQ9446gTAY3Gd/fxM4J4Xiv4b5RvmvmxL7794kYleouUMvapjK30x74fxc7Uf/8vj5PVZ+Nc5ZGkvQadQ3vlYgwvpiPiU78k4jN3cqQfFU2a5J4qXtjTl/llM5m0FxRyWjfMgk8EEPeVGBaVDF8dwDvhp3gpDsi9med5ZV0AnCIqem+XwBKU33TVseVfVKa5sDxTRh8oAdnG3QtJDQTBgio/HdImVYHpZWwRU77mOhhlxrf jRHDSMsZ 2sCNCD0K1xvZo+2HOlHjYKi63lQI4NPOQSp/kqy2rEgmZwwkqKMrxDeRqAR7voZupElPfnCXHHIHZOT3yIUKG2V3qBfHOVndHRgiCntb8HurO4LHYXmvVH/7X59FFIobDgKpi4MmCNVHR3gX/l2Kh6cw/vcRP4X6Qk+z0yUkUrstMFmFNACJ9qZwCsVYQrhkOXT25UqKjr2wc+xQ1eKzsPqNCXKbnmeFxx60v3ZbVfkZlzGzjfsjbLQpkbhQcB4l90LPvShN6/E9PZFFnJwuALEakwN0DRS9jfQLt8qxi5BjhD86xk6GYDwZUXY4vr7ilv5o8CHRHfil4/yjQwVJGndVKBzzBhwrSDcEV2DYka1qRJ0g1RmQVk2DnU5Q0oyXYbP6uv/r0gXGdZqB5lTRyuOqztIlVLIgdmntPrsWSVEJKnTF05n1bm1ERxgVAmuZRHxiP/B4ae1xXHxnom5Gpsa6cFQ== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Expose a new register type NT_RISCV_USER_CFI for risc-v cfi status and state. Intentionally both landing pad and shadow stack status and state are rolled into cfi state. Creating two different NT_RISCV_USER_XXX would not be useful and wastage of a note type. Enabling or disabling of feature is not allowed via ptrace set interface. However setting `elp` state or setting shadow stack pointer are allowed via ptrace set interface. It is expected `gdb` might have use to fixup `elp` state or `shadow stack` pointer. Signed-off-by: Deepak Gupta --- arch/riscv/include/uapi/asm/ptrace.h | 18 ++++++++ arch/riscv/kernel/ptrace.c | 83 ++++++++++++++++++++++++++++++++++++ include/uapi/linux/elf.h | 1 + 3 files changed, 102 insertions(+) diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi/asm/ptrace.h index 659ea3af5680..e6571fba8a8a 100644 --- a/arch/riscv/include/uapi/asm/ptrace.h +++ b/arch/riscv/include/uapi/asm/ptrace.h @@ -131,6 +131,24 @@ struct __sc_riscv_cfi_state { unsigned long ss_ptr; /* shadow stack pointer */ }; +struct __cfi_status { + /* indirect branch tracking state */ + __u64 lp_en : 1; + __u64 lp_lock : 1; + __u64 elp_state : 1; + + /* shadow stack status */ + __u64 shstk_en : 1; + __u64 shstk_lock : 1; + + __u64 rsvd : sizeof(__u64) - 5; +}; + +struct user_cfi_state { + struct __cfi_status cfi_status; + __u64 shstk_ptr; +}; + #endif /* __ASSEMBLY__ */ #endif /* _UAPI_ASM_RISCV_PTRACE_H */ diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c index ea67e9fb7a58..df8b7c6ab671 100644 --- a/arch/riscv/kernel/ptrace.c +++ b/arch/riscv/kernel/ptrace.c @@ -19,6 +19,7 @@ #include #include #include +#include enum riscv_regset { REGSET_X, @@ -31,6 +32,9 @@ enum riscv_regset { #ifdef CONFIG_RISCV_ISA_SUPM REGSET_TAGGED_ADDR_CTRL, #endif +#ifdef CONFIG_RISCV_USER_CFI + REGSET_CFI, +#endif }; static int riscv_gpr_get(struct task_struct *target, @@ -184,6 +188,75 @@ static int tagged_addr_ctrl_set(struct task_struct *target, } #endif +#ifdef CONFIG_RISCV_USER_CFI +static int riscv_cfi_get(struct task_struct *target, + const struct user_regset *regset, + struct membuf to) +{ + struct user_cfi_state user_cfi; + struct pt_regs *regs; + + regs = task_pt_regs(target); + + user_cfi.cfi_status.lp_en = is_indir_lp_enabled(target); + user_cfi.cfi_status.lp_lock = is_indir_lp_locked(target); + user_cfi.cfi_status.elp_state = (regs->status & SR_ELP); + + user_cfi.cfi_status.shstk_en = is_shstk_enabled(target); + user_cfi.cfi_status.shstk_lock = is_shstk_locked(target); + user_cfi.shstk_ptr = get_active_shstk(target); + + return membuf_write(&to, &user_cfi, sizeof(user_cfi)); +} + +/* + * Does it make sense to allowing enable / disable of cfi via ptrace? + * Not allowing enable / disable / locking control via ptrace for now. + * Setting shadow stack pointer is allowed. GDB might use it to unwind or + * some other fixup. Similarly gdb might want to suppress elp and may want + * to reset elp state. + */ +static int riscv_cfi_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int ret; + struct user_cfi_state user_cfi; + struct pt_regs *regs; + + regs = task_pt_regs(target); + + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &user_cfi, 0, -1); + if (ret) + return ret; + + /* + * Not allowing enabling or locking shadow stack or landing pad + * There is no disabling of shadow stack or landing pad via ptrace + * rsvd field should be set to zero so that if those fields are needed in future + */ + if (user_cfi.cfi_status.lp_en || user_cfi.cfi_status.lp_lock || + user_cfi.cfi_status.shstk_en || user_cfi.cfi_status.shstk_lock || + !user_cfi.cfi_status.rsvd) + return -EINVAL; + + /* If lpad is enabled on target and ptrace requests to set / clear elp, do that */ + if (is_indir_lp_enabled(target)) { + if (user_cfi.cfi_status.elp_state) /* set elp state */ + regs->status |= SR_ELP; + else + regs->status &= ~SR_ELP; /* clear elp state */ + } + + /* If shadow stack enabled on target, set new shadow stack pointer */ + if (is_shstk_enabled(target)) + set_active_shstk(target, user_cfi.shstk_ptr); + + return 0; +} +#endif + static const struct user_regset riscv_user_regset[] = { [REGSET_X] = { .core_note_type = NT_PRSTATUS, @@ -224,6 +297,16 @@ static const struct user_regset riscv_user_regset[] = { .set = tagged_addr_ctrl_set, }, #endif +#ifdef CONFIG_RISCV_USER_CFI + [REGSET_CFI] = { + .core_note_type = NT_RISCV_USER_CFI, + .align = sizeof(__u64), + .n = sizeof(struct user_cfi_state) / sizeof(__u64), + .size = sizeof(__u64), + .regset_get = riscv_cfi_get, + .set = riscv_cfi_set, + }, +#endif }; static const struct user_regset_view riscv_user_native_view = { diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index b44069d29cec..b9daed4ab780 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -452,6 +452,7 @@ typedef struct elf64_shdr { #define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */ #define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */ #define NT_RISCV_TAGGED_ADDR_CTRL 0x902 /* RISC-V tagged address control (prctl()) */ +#define NT_RISCV_USER_CFI 0x903 /* RISC-V shadow stack state */ #define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */ #define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */ #define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension registers */