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Tue, 04 Feb 2025 17:21:59 -0800 (PST) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72fe69cec0fsm11457202b3a.137.2025.02.04.17.21.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Feb 2025 17:21:59 -0800 (PST) From: Deepak Gupta Date: Tue, 04 Feb 2025 17:21:50 -0800 Subject: [PATCH v9 03/26] riscv: zicfiss / zicfilp enumeration MIME-Version: 1.0 Message-Id: <20250204-v5_user_cfi_series-v9-3-b37a49c5205c@rivosinc.com> References: <20250204-v5_user_cfi_series-v9-0-b37a49c5205c@rivosinc.com> In-Reply-To: <20250204-v5_user_cfi_series-v9-0-b37a49c5205c@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Deepak Gupta X-Mailer: b4 0.14.0 X-Rspam-User: X-Rspamd-Server: rspam01 X-Rspamd-Queue-Id: 1536940008 X-Stat-Signature: zoiigqjgdpucd95dsmn4a6mfo3j743ij X-HE-Tag: 1738718520-406715 X-HE-Meta: U2FsdGVkX180IAgWwoSen6lQ9V5rcsqPK2WM7qL/VfnBstwtwdxcnPxazcwYAwAMhnu8tjt9I+Ira0+z7l6aO6zxKiowIBOnLKzsaxPADza9LnAa6b107xFaBL03KnYNCBIzAbp5YhhwDv2gyxh03tIAdgetU3MwpGEsjPEuHIwtEzGw2CGjx+c0Y5VDupBxgiSgGIHEpzzI3hWZp/FCxrNi3P1k6Zc6h4sDtPiEgKObtxT+eb8ehuoEwlnnoXG4yjabuqoWvWksv+QvefrrepcD+Wd9rFELyGohTgyzRDlAhCcyE/GcWLpgvQKAfhmGymcYCGUXXHU2hT85sUAtk2xvPZI+O9cjuBGU729ZpEeYGRst823VM3je44p5bIPJyB++nl1KrhrnHajvzGEL1UjNY323e3yGmH0kzJwdZiVSZXnE1GdyhDDRiSy8PJzJMYZaNuw8XCfJyWYV0rnn+/GR648ACF6cw4Yzyfr54B+dyxTlhLvZngzoyYoRxWHQMvuiI4irfq9HqICLfu5ht566Dz31MHQQL6pyjKUxMj1iUk4iqqQu5vApforEW8p3JXQpvNAFNTAnKyZz2l3KlBM5NqNs8xaXeiWFh3uGO38oV7wQoBdIB6saz/rW6QFFUMDfAq8AVX8LE9NB8f9YjrJNoq8KIIwpOvd2gRuaQh9sZKKF1zDSilidXRcKRYC6opcRuvAFzDEuaPNC+BilnbW3F14OTpc4xAmO+RPp7e0kJeCxjHjYNsqWDLkE0xnL49ZxQvtPDrrqVeFU6tpy88mLOZhTMkX6DL4XMQEBB0RyPDeRR/36FXd7vcQURTh/cocsBKABtcU3q7vNNCqovTHa/jENb/Xz8db7L6SaJoGKa8YtX0a6wRR2LRqzcD3kkehfGWQhrjuIhuXjkwaCAHXpznImUv74XmENdLCOHy3ERzmnNcjgYvMwGOQaNHsm74GtaIVgmKzUnAPYxdk rb14a4Y2 2BfSpf8gXtexxC43SH2H/rHHzbujmdws+F8Wu+euae4t4RgqZxEQgudzqis6u7h0AdaRTi9xW7RbhZkzm/z+Z1nkD+sIGyT9JgCS57wxKZ9wJiQEKFyEGiycVGL5Lppz2/PA99lBOn4LtnDz7TYhsSOigaBANUhyvdz68JnVi8pS2pCVDb3Fa3iPseQaKu5xDkTEA5wknwyn5UY9P3TS24zTtNLFfwXJTWMQ6vlLFh/Y+JL+DJfQ/g2lStZ90f698si/zu3Q7cPU8brTMBafwYa+rRuxzha/j8nOX3uWO58j84L/04ipZpbyZa7sl3FhPkTIol1tLFUHzdcOgCEbB/nMRPZfbRVkYxd99spy0G8r78umYeByu07MrBMSKjN4Ao4K8+GhmGrkdJ/Hl++vDI/7eNgX1djUbZIQKRdFtSiDCUSPKN0MHSJVtWtpCWppGxR0HsqN/Y+Q8rrXGB/VmF2DyhhJZUrV4LKleQ9C6AJAPmWBL90fA7K9VVw== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: This patch adds support for detecting zicfiss and zicfilp. zicfiss and zicfilp stands for unprivleged integer spec extension for shadow stack and branch tracking on indirect branches, respectively. This patch looks for zicfiss and zicfilp in device tree and accordinlgy lights up bit in cpu feature bitmap. Furthermore this patch adds detection utility functions to return whether shadow stack or landing pads are supported by cpu. Signed-off-by: Deepak Gupta --- arch/riscv/include/asm/cpufeature.h | 13 +++++++++++++ arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/include/asm/processor.h | 1 + arch/riscv/kernel/cpufeature.c | 2 ++ 4 files changed, 18 insertions(+) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index 569140d6e639..69007b8100ca 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -137,4 +138,16 @@ static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsi return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); } +static inline bool cpu_supports_shadow_stack(void) +{ + return (IS_ENABLED(CONFIG_RISCV_USER_CFI) && + riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICFISS)); +} + +static inline bool cpu_supports_indirect_br_lp_instr(void) +{ + return (IS_ENABLED(CONFIG_RISCV_USER_CFI) && + riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICFILP)); +} + #endif diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 869da082252a..2dc4232bdb3e 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -100,6 +100,8 @@ #define RISCV_ISA_EXT_ZICCRSE 91 #define RISCV_ISA_EXT_SVADE 92 #define RISCV_ISA_EXT_SVADU 93 +#define RISCV_ISA_EXT_ZICFILP 94 +#define RISCV_ISA_EXT_ZICFISS 95 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 5f56eb9d114a..e3aba3336e63 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -13,6 +13,7 @@ #include #include +#include #define arch_get_mmap_end(addr, len, flags) \ ({ \ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c6ba750536c3..e72de12e5b99 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -333,6 +333,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xlinuxenvcfg_exts, riscv_ext_zicboz_validate), __RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE), + __RISCV_ISA_EXT_SUPERSET(zicfilp, RISCV_ISA_EXT_ZICFILP, riscv_xlinuxenvcfg_exts), + __RISCV_ISA_EXT_SUPERSET(zicfiss, RISCV_ISA_EXT_ZICFISS, riscv_xlinuxenvcfg_exts), __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),