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a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1738719723; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MJZfFPcR2XnyePdMtSV8xYvGCnHjzZ83M+Symc/4Er0=; b=HiV8dGAJdlvQ4MWzeEl8GDv5AH4aiqkl40IuX2/ZLHOS4ezF5GGmy0rFPZSRsJbbmmA4VG /oxIcx7hiGCMruauUQoJR7+LOQLEwMdnOiAYyRJaA3+Qk0SuotBzd37Uyyqryuz642w6ye yKsLtaBfbvpo0mMy2kQ1ZyiaYpOQC/Q= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tfUP4-000000004Cs-2jje; Tue, 04 Feb 2025 20:40:34 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Rik van Riel , Manali Shukla Subject: [PATCH v8 04/12] x86/mm: get INVLPGB count max from CPUID Date: Tue, 4 Feb 2025 20:39:53 -0500 Message-ID: <20250205014033.3626204-5-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250205014033.3626204-1-riel@surriel.com> References: <20250205014033.3626204-1-riel@surriel.com> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Server: rspam01 X-Rspamd-Queue-Id: 8EEB812000D X-Stat-Signature: s5m17umhngmgkb1x4r814kyg4a31r816 X-HE-Tag: 1738719723-463647 X-HE-Meta: U2FsdGVkX1/3gEeAciviiUHf2bh1yLWSB9iikFCE8l8cN2lPW2jkYNtYxEhJG6G14iGIo4FwrIbk9Do+BeQRhfLvMm2Jkk7psMWmeounJtSbETLPxQ/yVTOtBqloGsYhYpd/wgZfWlvrk0/+ZH4EKEX+rcfl6t+5wTV8Sx+AgEsu2xt2Rf3mBT0FgGm3VUtqjOPadpDNHBU+YgEgRfO7ofeoTYc0AZIu5dt6QPpeFMOx3GNix4a3W20XJ/sLeSRzih57ktqm6D+ygVYOyjgbdoQqwQeHAmwfvCQF7T1uuPu0YITmdtpPmOYRZQAZdXz+M+N48WItDYjI6Y9c5ra5hNHYMzrV+Qrsa43StfCTha9sRSHLuDli4G4Gsnl27zlRBwrz1xAJBhaMA/0VrV0iWBpIKZ6pz5AhZ7YoTt8p1kSiLJLgM5aHuWabV2rbvp+QVgR2LvXOz35tfLlww7+NR0gl3sQrZXqUGyq/XKRKcbaz7BupcF0bnGk3TPKdDf3kkS8yH0K4MHln6mTCpw6J/XGcFMNS4+bwovRf5S+iGMvTHrhgWrwq4skf8oXxmZzyIhuJrP/zCdMm2Mz3ZiKplcigIayDcoHghDCPO2OoqhAHCgw/j14PMYhbOzPkfuhY9x+I54tSxfD5codgC2LslyBTGiVh+soEk+WrO3O80g2odjXXnbUnsI5Y6IE2vqH9FsMxzVRvXAWQ99HYH6rzCTCe71YxW2bldN+BoFTjwegkke1Rn1Ndy9dFyC/JDICccmLTpxfnGoYZet99OPojp7Wyp7le5AQW9apvP+BolaUHCQ+RBvDMHdh5oytjkVuEiv7PmHU9KgDuaHO+wnEquWz6oOLedg0df8tsuhSRIv0GUA9HMS/rGToQ25p/nSG37dJodyD4dbWFGURVFeqdTQmCXTHReT+BWoaLbPZkjtYanzym/Cy4h6KYtllHY6e5UiRwEovpVnvrCDkQSlO 2J+wi+2U uwQbFgKADJGzABPCacpZX3LsUtdXiIL7kFL8Wi3al5PmAqSavofrWN0H4RUxeqA6+D6Gt6VbA8eedcxdqK2uHY/ygTTNybPl1LejeFWp2whDHVdAtnXMusVpgs8PB00OyrB21CzLsM12mgs/Mb/VCvLtzG6VyiqjHSsoYDgMownypoQeJdzRbFvko30GV3mKrl+TQL7Yz81526GdVBo1151BViZFDy8KlrQg9Fpc0m78p5D0O4katnojnm4gJHgXiWbxjiHRi35TbGlE0VZU8vMYb4GsiWrBUykVQOhfmm7k2lRsfGVK6UA8l8jbHp71Mcj6NOgywjt6dpt1btp9B4WT2cvlDy6W5Go4gfcmvDV9c96sBMNxItMYdKvzfhmBpnu02O3Q2DVqURYgIBp1nICl6ayzjFBNZCVwXZB7hq08W36Fdqf64vszfHxjOyTPsAvfW8LHfRkuNTKqMdSsY3t1CYInbpg8iiEB1xyPxo3NEq2yBt+teWBpRHw== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: The CPU advertises the maximum number of pages that can be shot down with one INVLPGB instruction in the CPUID data. Save that information for later use. Signed-off-by: Rik van Riel Tested-by: Manali Shukla --- arch/x86/Kconfig.cpu | 5 +++++ arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/tlbflush.h | 7 +++++++ arch/x86/kernel/cpu/amd.c | 8 ++++++++ 4 files changed, 21 insertions(+) diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 2a7279d80460..abe013a1b076 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -395,6 +395,10 @@ config X86_VMX_FEATURE_NAMES def_bool y depends on IA32_FEAT_CTL +config X86_BROADCAST_TLB_FLUSH + def_bool y + depends on CPU_SUP_AMD && 64BIT + menuconfig PROCESSOR_SELECT bool "Supported processor vendors" if EXPERT help @@ -431,6 +435,7 @@ config CPU_SUP_CYRIX_32 config CPU_SUP_AMD default y bool "Support AMD processors" if PROCESSOR_SELECT + select X86_BROADCAST_TLB_FLUSH help This enables detection, tunings and quirks for AMD processors diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 17b6590748c0..f9b832e971c5 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -338,6 +338,7 @@ #define X86_FEATURE_CLZERO (13*32+ 0) /* "clzero" CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* "irperf" Instructions Retired Count */ #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* "xsaveerptr" Always save/restore FP error pointers */ +#define X86_FEATURE_INVLPGB (13*32+ 3) /* INVLPGB and TLBSYNC instruction supported. */ #define X86_FEATURE_RDPRU (13*32+ 4) /* "rdpru" Read processor register at user level */ #define X86_FEATURE_WBNOINVD (13*32+ 9) /* "wbnoinvd" WBNOINVD instruction */ #define X86_FEATURE_AMD_IBPB (13*32+12) /* Indirect Branch Prediction Barrier */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 02fc2aa06e9e..8fe3b2dda507 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -183,6 +183,13 @@ static inline void cr4_init_shadow(void) extern unsigned long mmu_cr4_features; extern u32 *trampoline_cr4_features; +/* How many pages can we invalidate with one INVLPGB. */ +#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH +extern u16 invlpgb_count_max; +#else +#define invlpgb_count_max 1 +#endif + extern void initialize_tlbstate_and_flush(void); /* diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 79d2e17f6582..bcf73775b4f8 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -29,6 +29,8 @@ #include "cpu.h" +u16 invlpgb_count_max __ro_after_init; + static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) { u32 gprs[8] = { 0 }; @@ -1135,6 +1137,12 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) tlb_lli_2m[ENTRIES] = eax & mask; tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; + + /* Max number of pages INVLPGB can invalidate in one shot */ + if (boot_cpu_has(X86_FEATURE_INVLPGB)) { + cpuid(0x80000008, &eax, &ebx, &ecx, &edx); + invlpgb_count_max = (edx & 0xffff) + 1; + } } static const struct cpu_dev amd_cpu_dev = {