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b=gGkuDiBDS4ihmNFZkFNOYw2RY+F3FANpHOmoSeyaCYLK5yMJs9XZXTycyDc5aMOfSNkSWC KTrb01dd1VChOe52TX4uwCY59TyU6jeKJH+1uhq8le5bITNmMP/CBVSalv0L8/IRR4u862 eSjjFTfFLLKKC3F2hudw5T5RTpc25JQ= ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1738719721; a=rsa-sha256; cv=none; b=xwOfIt/6+ADPy+x8f1GUNB/IhmjZiA8yblztXTOG7Z1UdWYliMzIdD8QZEPRVQK33LoURk wo4eER7lhl6pqtJSb3WisBhw9jICOVrDdZg8mVvR4xlu3qH7iVvysCZoNdPw5hzzTD7MvD JLRhAI+y9cBa1L1E+YX36KsqnD4m4tk= ARC-Authentication-Results: i=1; imf18.hostedemail.com; dkim=none; spf=pass (imf18.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com; dmarc=none Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tfUP4-000000004Cs-2p3a; Tue, 04 Feb 2025 20:40:34 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Rik van Riel , Manali Shukla Subject: [PATCH v8 05/12] x86/mm: add INVLPGB support code Date: Tue, 4 Feb 2025 20:39:54 -0500 Message-ID: <20250205014033.3626204-6-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250205014033.3626204-1-riel@surriel.com> References: <20250205014033.3626204-1-riel@surriel.com> MIME-Version: 1.0 X-Stat-Signature: ef4n9awdgx6i6yaaw84nwnw3zfijy8yk X-Rspamd-Queue-Id: 65B721C0005 X-Rspam-User: X-Rspamd-Server: rspam06 X-HE-Tag: 1738719721-895408 X-HE-Meta: U2FsdGVkX181dRusCatOb+y5+9SBBz07poA6RPkgGQDY6Roh97638/rZB/Q7vMhv9MQcuhsF3GenU014Wsbb2viTBxvweYF0tfEpVVcUREQrqmx9TAaoyMh+dsEraii0zKEgCq6qxqq/h/zWttXAbfpzVFOhq8Khso0JxPfzl1SHHMwwlGWYujaOPzepG2yEFUPYL2KUZw58s3d74RgQb5YY6xOlsNc6kQfhn6/bUS2LXOjQ2l7ZRKTeSbCmUI2LorL3akFuHrBMG75sTldy01CwZOs3NfejypIihnVEu024Xxyj30wRHj2lyx7Z/fFlZoTPXGTNSMoUygeAgZJQThM68tQ6QLIhu/KfBJn1TzIay/L8FckuV+XYiJVH4LnM4HTP51PPLZpvNtkkYZ8O8ENcYo+XtfvnxcdSwVzCwdyINN1rao2CQM7491rR8uOUSNuoA/nY3mOMK8XKI641j61rY4m4w/u4NNZ5pRGbO2NjN5QMRyo28JucwJQGKrGIg0rLpn1wnM9h8tM8OktXFydFA5OwmF9ySZqoR9su3V1paaTRCqyGdmJ2WczZfLSFFltHYtr2v5ptRcyQ2H8z8SPjpRrCVd+Q6ZzVM/m+D/omhl9fP5NnqI3p+cEOJ9DT38dcdPkNXFJ9UetymEpBI4IeFZTnysnD8Ap777De2KIHmL7YCHSvKb44chiTkn8Kied/LITU5Pd2e02FAH0GBVG5mlXTuV/5zaPQK5gIJuumCQ5r5Iwa/g2pUnj7BSSOPQFAxdCs5zkSPUAbSVmm+w8xS1ZnbY1McKNavF14S7m3mpb3dHA1wp7dfWKPtZax+5xrqBLCjNIpK/0vJemPWK59mZ+ss7IIjlr57fpZUok5LxYo1jjq/XADQSJ+YakxqJKyEaSB2Gc9qR/ey1rKyaFrB/OsyOsi0YiWQUkYtASk1FoTjzXwzvBtwfFLySRIEKKnZMR5Q6FLcWHPajV yK373Z6e gUplkAULtyLVkYhLvBuOfsOGSgJWim+I+/V5Ewg9mktzyzvt9aqZwdgdAN0VHDWcHl4mnwvJPTIWwJkKZY9aaFTzyMbkXI21ddOE9vQkplsG2yLZFr8miKWkTCisaitEpIYHaA1ECpWvfoGadgm6eCqyMGmH6IRGwvjvrJMnme5FMoZGkjqIpbmw7s2lFbI+zguZx2/xRVwl2+z0ynj2/vv0TTo8I9dYb1MolrcmUkYNHFz14XW0QVIYpgLxcD2CtIShka7GsnVPbY+m9HdrDuOnOTdvced3Nb3BjJouIQSSyQPaxvRMu+ORi5HmX6q1MweIqSXiRAPIMFQWS+l3ZGjnsaTUr2hqu6m5GSa+icw4N2wHaIr1WE3i0P5Sc3ip7M35D1Jc0SPdUswt34jipEd9SVLx6vCXgM8QJVHKKI0gB3nxPxNwTll3eaBuQjsfDkKR+6ojlveI0TACNq4LZvWI6nDGYspC2cHNAjC+5O22RySZMkxDo0qT3Yg== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Add invlpgb.h with the helper functions and definitions needed to use broadcast TLB invalidation on AMD EPYC 3 and newer CPUs. Signed-off-by: Rik van Riel Tested-by: Manali Shukla --- arch/x86/include/asm/invlpgb.h | 101 ++++++++++++++++++++++++++++++++ arch/x86/include/asm/tlbflush.h | 1 + 2 files changed, 102 insertions(+) create mode 100644 arch/x86/include/asm/invlpgb.h diff --git a/arch/x86/include/asm/invlpgb.h b/arch/x86/include/asm/invlpgb.h new file mode 100644 index 000000000000..a1d5dedd5217 --- /dev/null +++ b/arch/x86/include/asm/invlpgb.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_INVLPGB +#define _ASM_X86_INVLPGB + +#include +#include +#include + +/* + * INVLPGB does broadcast TLB invalidation across all the CPUs in the system. + * + * The INVLPGB instruction is weakly ordered, and a batch of invalidations can + * be done in a parallel fashion. + * + * TLBSYNC is used to ensure that pending INVLPGB invalidations initiated from + * this CPU have completed. + */ +static inline void __invlpgb(unsigned long asid, unsigned long pcid, + unsigned long addr, u16 extra_count, + bool pmd_stride, u8 flags) +{ + u32 edx = (pcid << 16) | asid; + u32 ecx = (pmd_stride << 31) | extra_count; + u64 rax = addr | flags; + + /* The low bits in rax are for flags. Verify addr is clean. */ + VM_WARN_ON_ONCE(addr & ~PAGE_MASK); + + /* INVLPGB; supported in binutils >= 2.36. */ + asm volatile(".byte 0x0f, 0x01, 0xfe" : : "a" (rax), "c" (ecx), "d" (edx)); +} + +/* Wait for INVLPGB originated by this CPU to complete. */ +static inline void tlbsync(void) +{ + cant_migrate(); + /* TLBSYNC: supported in binutils >= 0.36. */ + asm volatile(".byte 0x0f, 0x01, 0xff" ::: "memory"); +} + +/* + * INVLPGB can be targeted by virtual address, PCID, ASID, or any combination + * of the three. For example: + * - INVLPGB_VA | INVLPGB_INCLUDE_GLOBAL: invalidate all TLB entries at the address + * - INVLPGB_PCID: invalidate all TLB entries matching the PCID + * + * The first can be used to invalidate (kernel) mappings at a particular + * address across all processes. + * + * The latter invalidates all TLB entries matching a PCID. + */ +#define INVLPGB_VA BIT(0) +#define INVLPGB_PCID BIT(1) +#define INVLPGB_ASID BIT(2) +#define INVLPGB_INCLUDE_GLOBAL BIT(3) +#define INVLPGB_FINAL_ONLY BIT(4) +#define INVLPGB_INCLUDE_NESTED BIT(5) + +/* Flush all mappings for a given pcid and addr, not including globals. */ +static inline void invlpgb_flush_user(unsigned long pcid, + unsigned long addr) +{ + __invlpgb(0, pcid, addr, 0, 0, INVLPGB_PCID | INVLPGB_VA); + tlbsync(); +} + +static inline void invlpgb_flush_user_nr_nosync(unsigned long pcid, + unsigned long addr, + u16 nr, + bool pmd_stride) +{ + __invlpgb(0, pcid, addr, nr - 1, pmd_stride, INVLPGB_PCID | INVLPGB_VA); +} + +/* Flush all mappings for a given PCID, not including globals. */ +static inline void invlpgb_flush_single_pcid_nosync(unsigned long pcid) +{ + __invlpgb(0, pcid, 0, 0, 0, INVLPGB_PCID); +} + +/* Flush all mappings, including globals, for all PCIDs. */ +static inline void invlpgb_flush_all(void) +{ + __invlpgb(0, 0, 0, 0, 0, INVLPGB_INCLUDE_GLOBAL); + tlbsync(); +} + +/* Flush addr, including globals, for all PCIDs. */ +static inline void invlpgb_flush_addr_nosync(unsigned long addr, u16 nr) +{ + __invlpgb(0, 0, addr, nr - 1, 0, INVLPGB_INCLUDE_GLOBAL); +} + +/* Flush all mappings for all PCIDs except globals. */ +static inline void invlpgb_flush_all_nonglobals(void) +{ + __invlpgb(0, 0, 0, 0, 0, 0); + tlbsync(); +} + +#endif /* _ASM_X86_INVLPGB */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 8fe3b2dda507..dba5caa4a9f4 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include