From patchwork Thu Feb 6 04:43:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13962188 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BFA2C02196 for ; Thu, 6 Feb 2025 04:55:14 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id A555A6B0083; Wed, 5 Feb 2025 23:55:13 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id A052C6B0085; Wed, 5 Feb 2025 23:55:13 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 8CC3F6B0088; Wed, 5 Feb 2025 23:55:13 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0013.hostedemail.com [216.40.44.13]) by kanga.kvack.org (Postfix) with ESMTP id 6F4336B0083 for ; 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b=6dhjLIVGu7W/c5NPwU/yOfNN9rrWSsw4QcSEhedX3kKg67YbZb502Hnvwwf/KPL8aQ4wBH 8KZcqu84fk48hRuhZp3TlPyCeyOBQhv0rBhzMIl2IYNMy8LIzo5ZWHlDwqQUPZYb5dZrcC onniP0iah7sIeiqQTMzZtOYL0u3m0ro= ARC-Authentication-Results: i=1; imf18.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf18.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1738817711; a=rsa-sha256; cv=none; b=rzAb9akHyaO1EAaHjVwv7/ZKhQMHSE97N+ksJxwTyslMIexOSjMtqEmQofnutHt5d53vA2 IP4nMPwj4cjMeXI2KYgf4e0NwqM92lvYJq6vvva+qJNg+ooAYtSuWnUjHQqB2Nxva1voIX Y+g7rDB/SDqPptC1usaN2Tf5vqJrQis= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tftjw-000000004tQ-2igC; Wed, 05 Feb 2025 23:43:48 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Rik van Riel , Manali Shukla Subject: [PATCH v9 10/12] x86/mm: do targeted broadcast flushing from tlbbatch code Date: Wed, 5 Feb 2025 23:43:29 -0500 Message-ID: <20250206044346.3810242-11-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206044346.3810242-1-riel@surriel.com> References: <20250206044346.3810242-1-riel@surriel.com> MIME-Version: 1.0 X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: 7C9411C0007 X-Stat-Signature: yzn6k69omq18rnexadpb4bqniqi8wni4 X-Rspam-User: X-HE-Tag: 1738817711-497525 X-HE-Meta: U2FsdGVkX19wd+HH21MTMeUqon9xh+FWHG0yFBNWBeBu5tvi6SZQpoL5jkdVSqxAxmqYnvduV6uIRe3BWtl9HcRFg2kK/fLeh159tfYoM6ZpJdCM1aJTnj5N93jA3bEl3pZfdjIZCSQl+n8oeLKFCEYOaefUTFigDvNKo6t7rYPqBSpvEF91w5vsZ9DOtU4N9KOKVYCJX0oYrSndQDpB/ztDknG+i3RV70h55beVJTjETmp6iZhmn5Ql5d8DKXu4YIGns3Fv5dDNCwLsH6uHb6km7Gt8pAZcNm5gV5r8mZjs5GTotpb20R/imSjWstJcmSjMvjAMXJeYxiCWweEngpxXWdAV+yIard32p28uJXTWiIjoIFOW9ciAAbu3AMrrmqJgZgLKc0PHPgh1Y4RnAqNWmz28sswOpQ9/EqHXWfRtivSCac7Tp7f+OfN10txHDefhG3iZ3x9ZC8MEsZ/7UutbNJdWnPLCB1Q4VVifJZRwjTjuluCWbPjSC7c5kwIqG7lvqpaqwYurAXkq4aFVvIYse2vikwBqZkHbU/goiCyn9PDqg17VzY5S7QrQdBtDeALqJpjAnixjXun664JYGTjIMBZZgaoBY8Oeyo23T/STDL26sNIszZwTkXtwUVHMvP4pnb4o5KWuHBPauflXcV7CjjETQb++2oAotwNL6cu5bufWqV5pab5l9nwGHC+I0cldePU4X4do1KJ936fmWr02lPkVb9JUvL//X2JRKr/jZaHiWDnteWR8SSc5dR4jZ68X7IS4BgmhWhUw4F2zbkgWsPsem9Z5vWliR3R4sslkyRThLeUMovcvwvDu5ROY2NTuulm1ipK7I9Diyf73Xs/HHHfnEGJKiqoWZrGg+TMCtxixI5917iMYnkF3mkk65MHS0EO2XzXYuF+sTnjJGidbhtBnjR5reqJnh0O7wybOaF/+KMuKb7tYW57F3QjIaLe5csQD5PXrnUBW5vg nNi1jACG 5XvNDLqjlW9djKEAvpkoKGJrhGvydokg5zDuIYThLEMpebJABUR05kFHk1CATukab2rY/5197GaPp54m9Frz/5W0BHweAgdToPlRYruvFZLb5sE7xhwtT1mUH42PFtqbixKKcq5b49ot9UrDUwEGxFwFe4zpBI3ODNn2K8MchDsbrolYmgIoK1OBHYC66uUp7fTkEQUZ4UNiUwfdJLCGBoNBhIdrQDJ2l138/hr/i+LcDpp4MEMD6Voz/2TDEccKeLeqoyPumjCHVwJBBUom93B8ZTLJxZGlJjBAmNB5dNGpDbVLrMZujeixdY3UwJ9Q8+KVqUI8XrsupCpVt44ihBAK8jHcjzKK25Iyoz0sp+GDVvCWv4P3k4OOiNKaD+28NT1gY5fVc9rj2/RojuVcZt6eWvpvIRdqK5V+7u3cGS3/3ZzAAiDwIr8ckhy4WqP+4deoSkHyWbCTdxNxWyV/oWvVEdqGShQOgohBxba0HL7mx9nrl705HVxQ/bw== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Instead of doing a system-wide TLB flush from arch_tlbbatch_flush, queue up asynchronous, targeted flushes from arch_tlbbatch_add_pending. This also allows us to avoid adding the CPUs of processes using broadcast flushing to the batch->cpumask, and will hopefully further reduce TLB flushing from the reclaim and compaction paths. Signed-off-by: Rik van Riel Tested-by: Manali Shukla --- arch/x86/include/asm/invlpgb.h | 21 +++++---- arch/x86/include/asm/tlbflush.h | 17 ++++--- arch/x86/mm/tlb.c | 80 +++++++++++++++++++++++++++++++-- 3 files changed, 95 insertions(+), 23 deletions(-) diff --git a/arch/x86/include/asm/invlpgb.h b/arch/x86/include/asm/invlpgb.h index a1d5dedd5217..357e3cc417e4 100644 --- a/arch/x86/include/asm/invlpgb.h +++ b/arch/x86/include/asm/invlpgb.h @@ -31,9 +31,8 @@ static inline void __invlpgb(unsigned long asid, unsigned long pcid, } /* Wait for INVLPGB originated by this CPU to complete. */ -static inline void tlbsync(void) +static inline void __tlbsync(void) { - cant_migrate(); /* TLBSYNC: supported in binutils >= 0.36. */ asm volatile(".byte 0x0f, 0x01, 0xff" ::: "memory"); } @@ -61,19 +60,19 @@ static inline void invlpgb_flush_user(unsigned long pcid, unsigned long addr) { __invlpgb(0, pcid, addr, 0, 0, INVLPGB_PCID | INVLPGB_VA); - tlbsync(); + __tlbsync(); } -static inline void invlpgb_flush_user_nr_nosync(unsigned long pcid, - unsigned long addr, - u16 nr, - bool pmd_stride) +static inline void __invlpgb_flush_user_nr_nosync(unsigned long pcid, + unsigned long addr, + u16 nr, + bool pmd_stride) { __invlpgb(0, pcid, addr, nr - 1, pmd_stride, INVLPGB_PCID | INVLPGB_VA); } /* Flush all mappings for a given PCID, not including globals. */ -static inline void invlpgb_flush_single_pcid_nosync(unsigned long pcid) +static inline void __invlpgb_flush_single_pcid_nosync(unsigned long pcid) { __invlpgb(0, pcid, 0, 0, 0, INVLPGB_PCID); } @@ -82,11 +81,11 @@ static inline void invlpgb_flush_single_pcid_nosync(unsigned long pcid) static inline void invlpgb_flush_all(void) { __invlpgb(0, 0, 0, 0, 0, INVLPGB_INCLUDE_GLOBAL); - tlbsync(); + __tlbsync(); } /* Flush addr, including globals, for all PCIDs. */ -static inline void invlpgb_flush_addr_nosync(unsigned long addr, u16 nr) +static inline void __invlpgb_flush_addr_nosync(unsigned long addr, u16 nr) { __invlpgb(0, 0, addr, nr - 1, 0, INVLPGB_INCLUDE_GLOBAL); } @@ -95,7 +94,7 @@ static inline void invlpgb_flush_addr_nosync(unsigned long addr, u16 nr) static inline void invlpgb_flush_all_nonglobals(void) { __invlpgb(0, 0, 0, 0, 0, 0); - tlbsync(); + __tlbsync(); } #endif /* _ASM_X86_INVLPGB */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 234277a5ef89..bf167e215e8e 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -106,6 +106,7 @@ struct tlb_state { * need to be invalidated. */ bool invalidate_other; + bool need_tlbsync; #ifdef CONFIG_ADDRESS_MASKING /* @@ -310,6 +311,10 @@ static inline void broadcast_tlb_flush(struct flush_tlb_info *info) static inline void consider_global_asid(struct mm_struct *mm) { } + +static inline void tlbsync(void) +{ +} #endif #ifdef CONFIG_PARAVIRT @@ -359,21 +364,15 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm) return atomic64_inc_return(&mm->context.tlb_gen); } -static inline void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, - struct mm_struct *mm, - unsigned long uaddr) -{ - inc_mm_tlb_gen(mm); - cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm)); - mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL); -} - static inline void arch_flush_tlb_batched_pending(struct mm_struct *mm) { flush_tlb_mm(mm); } extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch); +extern void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, + struct mm_struct *mm, + unsigned long uaddr); static inline bool pte_flags_need_flush(unsigned long oldflags, unsigned long newflags, diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 05390f0e6cb0..4253c3efd7e4 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -488,6 +488,37 @@ static void finish_asid_transition(struct flush_tlb_info *info) WRITE_ONCE(mm->context.asid_transition, false); } +static inline void tlbsync(void) +{ + if (!this_cpu_read(cpu_tlbstate.need_tlbsync)) + return; + __tlbsync(); + this_cpu_write(cpu_tlbstate.need_tlbsync, false); +} + +static inline void invlpgb_flush_user_nr_nosync(unsigned long pcid, + unsigned long addr, + u16 nr, bool pmd_stride) +{ + __invlpgb_flush_user_nr_nosync(pcid, addr, nr, pmd_stride); + if (!this_cpu_read(cpu_tlbstate.need_tlbsync)) + this_cpu_write(cpu_tlbstate.need_tlbsync, true); +} + +static inline void invlpgb_flush_single_pcid_nosync(unsigned long pcid) +{ + __invlpgb_flush_single_pcid_nosync(pcid); + if (!this_cpu_read(cpu_tlbstate.need_tlbsync)) + this_cpu_write(cpu_tlbstate.need_tlbsync, true); +} + +static inline void invlpgb_flush_addr_nosync(unsigned long addr, u16 nr) +{ + __invlpgb_flush_addr_nosync(addr, nr); + if (!this_cpu_read(cpu_tlbstate.need_tlbsync)) + this_cpu_write(cpu_tlbstate.need_tlbsync, true); +} + static void broadcast_tlb_flush(struct flush_tlb_info *info) { bool pmd = info->stride_shift == PMD_SHIFT; @@ -794,6 +825,8 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, if (IS_ENABLED(CONFIG_PROVE_LOCKING)) WARN_ON_ONCE(!irqs_disabled()); + tlbsync(); + /* * Verify that CR3 is what we think it is. This will catch * hypothetical buggy code that directly switches to swapper_pg_dir @@ -973,6 +1006,8 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, */ void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) { + tlbsync(); + if (this_cpu_read(cpu_tlbstate.loaded_mm) == &init_mm) return; @@ -1650,9 +1685,7 @@ void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) * a local TLB flush is needed. Optimize this use-case by calling * flush_tlb_func_local() directly in this case. */ - if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) { - invlpgb_flush_all_nonglobals(); - } else if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) { + if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) { flush_tlb_multi(&batch->cpumask, info); } else if (cpumask_test_cpu(cpu, &batch->cpumask)) { lockdep_assert_irqs_enabled(); @@ -1661,12 +1694,53 @@ void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) local_irq_enable(); } + /* + * If we issued (asynchronous) INVLPGB flushes, wait for them here. + * The cpumask above contains only CPUs that were running tasks + * not using broadcast TLB flushing. + */ + if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) + tlbsync(); + cpumask_clear(&batch->cpumask); put_flush_tlb_info(); put_cpu(); } +void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, + struct mm_struct *mm, + unsigned long uaddr) +{ + u16 asid = mm_global_asid(mm); + + if (asid) { + invlpgb_flush_user_nr_nosync(kern_pcid(asid), uaddr, 1, false); + /* Do any CPUs supporting INVLPGB need PTI? */ + if (static_cpu_has(X86_FEATURE_PTI)) + invlpgb_flush_user_nr_nosync(user_pcid(asid), uaddr, 1, false); + + /* + * Some CPUs might still be using a local ASID for this + * process, and require IPIs, while others are using the + * global ASID. + * + * In this corner case we need to do both the broadcast + * TLB invalidation, and send IPIs. The IPIs will help + * stragglers transition to the broadcast ASID. + */ + if (in_asid_transition(mm)) + asid = 0; + } + + if (!asid) { + inc_mm_tlb_gen(mm); + cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm)); + } + + mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL); +} + /* * Blindly accessing user memory from NMI context can be dangerous * if we're in the middle of switching the current user task or