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b=MsxWlkTF9HDCKYXDmMLpezWyuyIAk0eoUxrn47W0FFCcm5GFyDAKNC0VzKoKJwclpid+ns ptuRq5rebJGV8MRm0+HLmTwHH0T/RfyU6OPj6JpAZXhhy3A3VUNvFQKu0sB1JvmTP8JWj7 jKZRERLzCja09Xh1wTmoV2zoiP+SUMo= ARC-Authentication-Results: i=1; imf12.hostedemail.com; dkim=none; spf=pass (imf12.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com; dmarc=none ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1738817111; a=rsa-sha256; cv=none; b=e34Vrxj37/Q+H8OgsMEuWQpPC4j1Ho05cZApiZmkrzbN/H+1L6/C5I2CLRKgYZiRDC6NJd n9nIuA1fxsQ7GM54QtU4EHdrwbQkeENLyw3cjtdfiweYesEi9ntLBjmbzcX6DaeQ571gdL bp4qH4aFvJPJzU5oX22hmV9h+FqvbVk= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tftjw-000000004tQ-225I; Wed, 05 Feb 2025 23:43:48 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Rik van Riel , Manali Shukla Subject: [PATCH v9 04/12] x86/mm: get INVLPGB count max from CPUID Date: Wed, 5 Feb 2025 23:43:23 -0500 Message-ID: <20250206044346.3810242-5-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206044346.3810242-1-riel@surriel.com> References: <20250206044346.3810242-1-riel@surriel.com> MIME-Version: 1.0 X-Rspamd-Server: rspam02 X-Rspamd-Queue-Id: B2EA540009 X-Stat-Signature: nx1tpxhdgxr9t7hp4epkwzr44zez3o9h X-Rspam-User: X-HE-Tag: 1738817111-411771 X-HE-Meta: U2FsdGVkX18sa/a1RUaQuIGFQgKDTWuotdRHB1EDpOYUNXBpiKnfJ1A5zbbhvxBSZA0h1Caq9b//rOPu24r6CYvGpgyVR7WXQpbzzrbovfqZs/5hSdmFRi/9CTxRVQLJkas2v6LLpAFav4o4S2xLxDxm6OOasVuLLupAjKnW0TbqdxinhQtkkZyOs/gSht1wisreBxCZDeWuFI9O/NHVrFo4gc38UGy91SARgIVq/THejUhFdaSTNFQDlOfuvVFZ5xlBQWNf954Of9zZZ8CJr4H0z6t153M1v8RJwj5yMXWAvI3eGAnMUjJCJVR7uzcYLmvlGJ/grhop1DfV5cfdz40uYPXTGzpUTpHRTgSJfZvaYPcHp/qifVAOoWfZhMPknJK7vMCY9m6Hm+KG9qAdcWh9o96fuHT9T+wH+ANl4UNysuuz1TYj33lf9ws7FeArfEKRxe9fIz/eM+cEQJXxJlp4hGzktZDeKo93eaLDgW8XNAbigQl1Qt+HsWgvp51/BqgxysAXf1kolXXVBGT4USGOPDmPSl8Jsx+NBTvAwgz01N7bhKvlEo1+/hZe8Vii1uE/UjvIIpejqLkJW7t0EgDrV+Xe+Uf9RD5xdaBzRBbndgwlISZmhu75LfXk+nWNxUdfRJz5Jz9s13HqeL7ehvsX6baVYWXN/eOexGxhtqUmjoyRboXlE81YHwfNjjwKZEHV6Vz/6u7qc8rprw1pEKtmrS2Mfm3LOV5nwRZ3/RWvtnIbAmx0J09SPBmuEhe7Lzu/gQYTu9oYtknwzhe3ZVLnnvlsCY3nIQhmnEQ6d7PUh2NTCEMmG8diApsZ6YdQx8ivZB09xw+Zj1YCQi9lyO9ArjislZK/Iw6E7Utd4P7m9hkd2vZb1WPCRUAS1zuegAniZG4c1/jzMsQWCQU2L42cNsKdCS5IhypenXuqoFKMUAgr6F3WWpTAWZljRsgjCi67He8hxrUWy3aZutf O+2jgOsP twCOFIsPmPBVPjGNH434m5wdMDE/sKlLz/wD+iRB96UnMXOpr6HVH2l4LRYcLDPAg4uqhNR8r2JbS86eSSCJU7LiUPQ9dR8b60q2xta7IINOdhwC6fcJZp8/xuh/ee+bhlAx9mEkQF38IAAV75s/xNqTuuNTY++fjr23RTvlln3H/WOwq/OVqTLLRfNT+mn6cYrC8Uw5ILMZTjhy0YY1OwJiZ/V1jRGmSEoYm1T5KRHL6HYSj0JhCoszPzOvqsPJFipEltASkKlucpzwBoHRphRYcvzpsJXjxE4/FuA/Bs9/RkftoxzV+gNHFaKzsbJxYEUgg0D+41oaMqFB8sc1ALMCUTbIRfHxUXCPvaf9feeP0qGmLcBI6eFwl6T5balyt+RBsPGlj7UfFgSEKSsR6TF8lBCz1kbDs62sAHu3N+VXRPSdsir2sF1lNxRaNFzAzzddT90YElae1ZjKFGx7FZjdlQxxiOQm6oxn6FI+l5RoH+A5jiOCgA7c3aw== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: The CPU advertises the maximum number of pages that can be shot down with one INVLPGB instruction in the CPUID data. Save that information for later use. Signed-off-by: Rik van Riel Tested-by: Manali Shukla --- arch/x86/Kconfig.cpu | 5 +++++ arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/tlbflush.h | 7 +++++++ arch/x86/kernel/cpu/amd.c | 8 ++++++++ 4 files changed, 21 insertions(+) diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 2a7279d80460..abe013a1b076 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -395,6 +395,10 @@ config X86_VMX_FEATURE_NAMES def_bool y depends on IA32_FEAT_CTL +config X86_BROADCAST_TLB_FLUSH + def_bool y + depends on CPU_SUP_AMD && 64BIT + menuconfig PROCESSOR_SELECT bool "Supported processor vendors" if EXPERT help @@ -431,6 +435,7 @@ config CPU_SUP_CYRIX_32 config CPU_SUP_AMD default y bool "Support AMD processors" if PROCESSOR_SELECT + select X86_BROADCAST_TLB_FLUSH help This enables detection, tunings and quirks for AMD processors diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 17b6590748c0..f9b832e971c5 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -338,6 +338,7 @@ #define X86_FEATURE_CLZERO (13*32+ 0) /* "clzero" CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* "irperf" Instructions Retired Count */ #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* "xsaveerptr" Always save/restore FP error pointers */ +#define X86_FEATURE_INVLPGB (13*32+ 3) /* INVLPGB and TLBSYNC instruction supported. */ #define X86_FEATURE_RDPRU (13*32+ 4) /* "rdpru" Read processor register at user level */ #define X86_FEATURE_WBNOINVD (13*32+ 9) /* "wbnoinvd" WBNOINVD instruction */ #define X86_FEATURE_AMD_IBPB (13*32+12) /* Indirect Branch Prediction Barrier */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 02fc2aa06e9e..8fe3b2dda507 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -183,6 +183,13 @@ static inline void cr4_init_shadow(void) extern unsigned long mmu_cr4_features; extern u32 *trampoline_cr4_features; +/* How many pages can we invalidate with one INVLPGB. */ +#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH +extern u16 invlpgb_count_max; +#else +#define invlpgb_count_max 1 +#endif + extern void initialize_tlbstate_and_flush(void); /* diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 79d2e17f6582..bcf73775b4f8 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -29,6 +29,8 @@ #include "cpu.h" +u16 invlpgb_count_max __ro_after_init; + static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) { u32 gprs[8] = { 0 }; @@ -1135,6 +1137,12 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) tlb_lli_2m[ENTRIES] = eax & mask; tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; + + /* Max number of pages INVLPGB can invalidate in one shot */ + if (boot_cpu_has(X86_FEATURE_INVLPGB)) { + cpuid(0x80000008, &eax, &ebx, &ecx, &edx); + invlpgb_count_max = (edx & 0xffff) + 1; + } } static const struct cpu_dev amd_cpu_dev = {