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b=mJTBo5L4WVJLoatdz0oc08m19vF1+peO4ycM+VDfwtfdlH9GAzwM4ekBSMj0EVYtv67Yds 1wPHZa6zgFHPwXeTKxDUauTztV4bKzSU2GcrRtbQ2VCcAnLDvZLjKCKIeIm+uCGTI5Hz4/ XEUVtHbZEZ615VpmfzDsfkflT4mSWp0= ARC-Authentication-Results: i=1; imf19.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf19.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1738817110; a=rsa-sha256; cv=none; b=OlDXmB31BMCH/t7izrUMwAYKKPwH07xjxXhEVOtb1zWBA07U95Clx0iAOwC+asJ7H0HcGE gzTYQOkQt8A0AM+u+QhdrThZ0vfDQorxcUB0z8qj4Z/BK+F3CyFxNgxwYVS6sxw1Ztw8eq mmNeVdnFexEhkc+uKsCIFaXA+W7KImI= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tftjw-000000004tQ-27vB; Wed, 05 Feb 2025 23:43:48 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Rik van Riel , Manali Shukla Subject: [PATCH v9 05/12] x86/mm: add INVLPGB support code Date: Wed, 5 Feb 2025 23:43:24 -0500 Message-ID: <20250206044346.3810242-6-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250206044346.3810242-1-riel@surriel.com> References: <20250206044346.3810242-1-riel@surriel.com> MIME-Version: 1.0 X-Rspamd-Queue-Id: 43A3F1A0006 X-Stat-Signature: dybcyxod8rbynq1opp1yawmxtdmqdoky X-Rspamd-Server: rspam08 X-Rspam-User: X-HE-Tag: 1738817110-875427 X-HE-Meta: U2FsdGVkX18bSmP5DTShCG8XGDooNf03EWR/YtOqOu2Hmpysq5GMd9pBZGoYjcvwhGNLTkxNk2UKn0mHv9mQLY6/4rRvTrJKDr7E8KcwGUGWyB6Ar7r6zEfyUWDw2vgaFUmyg6KHHdVNgD9sCDeKAT/JHBraxMj5N/x1TM8mYIEx6wsWGR1rRYFi/KkabsCepm7Ho7cnJuM1NY6JiggIZ++Tpe+jQI+kjZgSmwetM85xoGjxN5SCSVyo/KTiUPs2Ge+XVX8NWYQ8HbaGdpmCLL6HVfwj1FazwdMjFpUI3jvyt0dMfnOGxkhzey0W4KOitzs/okKesWX6pe/S2nCAK88wBY446ifjj8idosYm56eQhXAfBH10MfxpONfb0hposwCP5TlgVqKnAbaficE+wxUMpvPKJyGmgxmtnvDdEgIR/s+1Srf2QdD4e1iAvI7rDgAdjQLX1HCt9YRnjwAt+HfmDGYxKX7Z/J+0gDtPoj1jYggJqRHaNuIfE2wWzKgRJhYEebu7liyy5Q12GZiASdEWSHngdwkcTpTWoLrfYAtdzjY/1kibh2KANG5TwGhEfpQ9EAcngE8lPfnyt0syheJAv3zYXnH48oabZDU4ozfzQekD1b5VSPYTeCalJH7ZJvgumfFIzRFBBmoCXwS85i+CqYqkZdCIyN4f9r9b/hQCZktJdD63reKu+rgeeoPttOFaSeEDHm0+727hwUUndI4B8oJTadggr+5YlDTf6VmIHrG2LYosATSBoOQxyYVFGgpovJBFISmb4CHix+xWmG0FX82dytvXrYtrTxot+ko5wbY6OPhSJoVLgBCBK1j4/Jgo0HOArB17rdhfh0Qql39XEz2DALToC7InmeVFvllMyr48vxcZyuOcIaP7VHCTg6HUxwT62LhQb+PVjL3RCQgVmVjV5FvuV4tuJEkTlWK91RaRW9GI7Uz8ht8vURFL7e2Xjq7U9CJr+5ie6VS m1+mSguH YJVo6l0oLR9GAlMLAUl8avIOOVFS4n00bHMMF+IKQP8hPY1wyah5dWT5ex94ypg81oDqhLWa8yFJiGrIOTb3NLiRSrhLje3h79vH/7+gdED6bdo4a0pZWWEutON6PgnJkpzPn1Jq+CulxG2NFxOoFi840kYWlCiOuj90ciYldCNfOu5h6UtNepVIX5Aozv6jSEQP+NKZoLYlmvFKJ2Mxb25FuqapHVsuWX+HRzKVwhyOcZq3V7boC4tLNu/4iEO4uSiZGTPY1iO1E+V2Pgl5VBB/I53kcKIibu5W03MS/LRWNlovfW0mU4NJuHIAHOkMP/Uw/EWMeEUXoZFUlV+HFJBHzB6DEx6cl+UYBuIRRC9+P+WxR0rCA7lwXDq9swK2tT34GAT1LizYAX8atwHFG1QOyswECCnIPEht5gknHATPhV5kQOxCLuCtxjCW+C4XA2lv8ka8a/H21pBqd4/IIhOgRwXzrPgWM897L2fKKKAmrxQCn6KYPPCfwIQ== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Add invlpgb.h with the helper functions and definitions needed to use broadcast TLB invalidation on AMD EPYC 3 and newer CPUs. Signed-off-by: Rik van Riel Tested-by: Manali Shukla --- arch/x86/include/asm/invlpgb.h | 101 ++++++++++++++++++++++++++++++++ arch/x86/include/asm/tlbflush.h | 1 + 2 files changed, 102 insertions(+) create mode 100644 arch/x86/include/asm/invlpgb.h diff --git a/arch/x86/include/asm/invlpgb.h b/arch/x86/include/asm/invlpgb.h new file mode 100644 index 000000000000..a1d5dedd5217 --- /dev/null +++ b/arch/x86/include/asm/invlpgb.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_INVLPGB +#define _ASM_X86_INVLPGB + +#include +#include +#include + +/* + * INVLPGB does broadcast TLB invalidation across all the CPUs in the system. + * + * The INVLPGB instruction is weakly ordered, and a batch of invalidations can + * be done in a parallel fashion. + * + * TLBSYNC is used to ensure that pending INVLPGB invalidations initiated from + * this CPU have completed. + */ +static inline void __invlpgb(unsigned long asid, unsigned long pcid, + unsigned long addr, u16 extra_count, + bool pmd_stride, u8 flags) +{ + u32 edx = (pcid << 16) | asid; + u32 ecx = (pmd_stride << 31) | extra_count; + u64 rax = addr | flags; + + /* The low bits in rax are for flags. Verify addr is clean. */ + VM_WARN_ON_ONCE(addr & ~PAGE_MASK); + + /* INVLPGB; supported in binutils >= 2.36. */ + asm volatile(".byte 0x0f, 0x01, 0xfe" : : "a" (rax), "c" (ecx), "d" (edx)); +} + +/* Wait for INVLPGB originated by this CPU to complete. */ +static inline void tlbsync(void) +{ + cant_migrate(); + /* TLBSYNC: supported in binutils >= 0.36. */ + asm volatile(".byte 0x0f, 0x01, 0xff" ::: "memory"); +} + +/* + * INVLPGB can be targeted by virtual address, PCID, ASID, or any combination + * of the three. For example: + * - INVLPGB_VA | INVLPGB_INCLUDE_GLOBAL: invalidate all TLB entries at the address + * - INVLPGB_PCID: invalidate all TLB entries matching the PCID + * + * The first can be used to invalidate (kernel) mappings at a particular + * address across all processes. + * + * The latter invalidates all TLB entries matching a PCID. + */ +#define INVLPGB_VA BIT(0) +#define INVLPGB_PCID BIT(1) +#define INVLPGB_ASID BIT(2) +#define INVLPGB_INCLUDE_GLOBAL BIT(3) +#define INVLPGB_FINAL_ONLY BIT(4) +#define INVLPGB_INCLUDE_NESTED BIT(5) + +/* Flush all mappings for a given pcid and addr, not including globals. */ +static inline void invlpgb_flush_user(unsigned long pcid, + unsigned long addr) +{ + __invlpgb(0, pcid, addr, 0, 0, INVLPGB_PCID | INVLPGB_VA); + tlbsync(); +} + +static inline void invlpgb_flush_user_nr_nosync(unsigned long pcid, + unsigned long addr, + u16 nr, + bool pmd_stride) +{ + __invlpgb(0, pcid, addr, nr - 1, pmd_stride, INVLPGB_PCID | INVLPGB_VA); +} + +/* Flush all mappings for a given PCID, not including globals. */ +static inline void invlpgb_flush_single_pcid_nosync(unsigned long pcid) +{ + __invlpgb(0, pcid, 0, 0, 0, INVLPGB_PCID); +} + +/* Flush all mappings, including globals, for all PCIDs. */ +static inline void invlpgb_flush_all(void) +{ + __invlpgb(0, 0, 0, 0, 0, INVLPGB_INCLUDE_GLOBAL); + tlbsync(); +} + +/* Flush addr, including globals, for all PCIDs. */ +static inline void invlpgb_flush_addr_nosync(unsigned long addr, u16 nr) +{ + __invlpgb(0, 0, addr, nr - 1, 0, INVLPGB_INCLUDE_GLOBAL); +} + +/* Flush all mappings for all PCIDs except globals. */ +static inline void invlpgb_flush_all_nonglobals(void) +{ + __invlpgb(0, 0, 0, 0, 0, 0); + tlbsync(); +} + +#endif /* _ASM_X86_INVLPGB */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 8fe3b2dda507..dba5caa4a9f4 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include