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b=Sa2J9WvPHPh6WTYPvN6uswx2MdRwrbbE64Y1850ks9HIBAar0y3tN+/jDnhbeemn6h6xlq j9Luh+PquskLrZ7pYFB0qzsW1pmZbaYkYLFvfU8MMmnTValTF5DSMagbwpKkUamZrBLBHO fdTOoxr/Hadd2XrB6/s1NknkRSbBVek= ARC-Authentication-Results: i=1; imf14.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf14.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1739308143; a=rsa-sha256; cv=none; b=du2sUyU2LSCUCNcPveAJyuZ5SdGVcQ+mI1w/lJk3vcvSXdTSd5rb31Iqa4345jXw/VOC2C Nv4W+VMNL+17FtIp21xzNgoOLuglGA7ME7gYcF/jqBJ7F9z6Qo8xpb6FlqtANF+v35T0/J Iu08KPzY4Q6QIRF0FFXQR8Zx1TJ1VF8= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1thxUX-000000008HU-2paU; Tue, 11 Feb 2025 16:08:25 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jackmanb@google.com, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Rik van Riel , Manali Shukla Subject: [PATCH v10 04/12] x86/mm: get INVLPGB count max from CPUID Date: Tue, 11 Feb 2025 16:07:59 -0500 Message-ID: <20250211210823.242681-5-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250211210823.242681-1-riel@surriel.com> References: <20250211210823.242681-1-riel@surriel.com> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Server: rspam08 X-Rspamd-Queue-Id: A6AFF10000B X-Stat-Signature: bg9bpzyiwefzxznbqh4xfp9rws4uj9f4 X-HE-Tag: 1739308143-164087 X-HE-Meta: U2FsdGVkX19zbayFS1cPparQVuCrMsdv4kbTqdZNKgRNrJCeFtWAd6nLxV2Nko29vlnqQKTXSNH62ealFfDBeAOjcOOZ4anPlBakNR7HLW0/F6ZnrCRD1TIv3+OnnF2QRol8zzcZaFxHCOVVRRzDPM+vKwUS9Waq4XsjP4YRoNEFxUei400ualGWW02XUMTjWscDX3lSp1RxNr2CoTliK0iqq4ITWBb3fYYdpLK9Xi2HuNUk2v8x1gKx+nyM3lux9HNy2NKwRfxdnsBVXBUQWiJXVI3FPOUK5ZiY+/97sD3nj+bx3Gm1/mC0XYlbhbNNniH/3XErtH5h7jF0D9PXSzkQyPu09AbaF2GItFVHQQXQaA7M22REO6qkdISKQjPwWc1OsI8wYQIztHPGimI0H3TpPNNtFqTa3kj+EHsqrInz3lgh3vGnlCMljyXcVp1JEGKzDnR4Jxxkb0aS2Z2+a0LxX/zcb+z0iWcjBzlsLFBvqxtb3Ht34p6I8R58boOixvsByhQfhBn5SIm5FqtS/+iec088f4ohMHrdJsPr/2UG5+AIegEF1f+METZqayQ6o037XJ3UP7DXZs8bYeDLVZrtYWtr5nuJ2yiNOo88UU/1dCc632cvuTQUec9jwfBv+R+mxKMS1xVrdZzseXKvNcAYbJ+/EkfsxzacEL3DFMRZUpvhZWRoNP4Caw8XSufIoeZ6JWiPgigiuZ05Wo7c0K4IcyPA/EwEzb+cXSMnCiwdCPhIuLQ1Yf4clCyccztWCUMmGx7t35F0ap7/w1JHl02Ju4cTibK6PMMNV/JsRLFFBrcezAfOAu00qNXj4J7Rsi8601OFEOVJV9B7dXSuwRBKDpxpwUIDUd9IjAeNqLDc1+yj90xsOEhUT3BuITGr/OBz3tkhcq/F1sz7WNfBrwE6wYPG8So70x992mPHwWYVSabIUedinTf+9PhICgO+Cd+8e7RMFtLXG6QjOvW 7WiadsD8 9K5zzgyNGfi5c/fS/9ojv4z9exNKgIX9uGgcE/jbYMpzHu0WREuA3t1I3L6TkirAw7Kq+ldViSPplw5mZrQP0mc4Wu1TM0t6TUopKYA5rBqMOvcIe/R73ZSMLk/Kqx4E8G+9yYnR0d7L/gNu4qJ51ZzJJunUsu2h17SfKkPb0v2RHEK5YQrqvovPyruilH0Xqb7GQfuudMkEUAfWwCEcjs85XS17vBbm+J7MJnKIEt2hOg5PM7oyE/ET3N2Ur0HO6ov3NBcJ8tjno7TmV/KH+z66muiNo2avpbQCz4wd9wfNjS508kj8h2Fk9u37auyHA+I7Fp7vuu70LhW53VNcs2RfsxlvC2JirzkrL3pPzkxfwUESmo5kckG0oiZFLy7HaK++0yp1lyu3g/ksm91y0idh5b/sB4xzrTYxs6EoU0hXWRI7th6kxFlXwMrKTqgD/xyUwkxAU62jwKm0G0xfr2NFmvr+yWQjEEdnyxhYnBbdjhnvEc1WYZzOg1IRAH/3YCUGmziaqTjgJyms= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: The CPU advertises the maximum number of pages that can be shot down with one INVLPGB instruction in the CPUID data. Save that information for later use. Signed-off-by: Rik van Riel Tested-by: Manali Shukla Tested-by: Brendan Jackman --- arch/x86/Kconfig.cpu | 5 +++++ arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/tlbflush.h | 7 +++++++ arch/x86/kernel/cpu/amd.c | 8 ++++++++ 4 files changed, 21 insertions(+) diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu index 2a7279d80460..abe013a1b076 100644 --- a/arch/x86/Kconfig.cpu +++ b/arch/x86/Kconfig.cpu @@ -395,6 +395,10 @@ config X86_VMX_FEATURE_NAMES def_bool y depends on IA32_FEAT_CTL +config X86_BROADCAST_TLB_FLUSH + def_bool y + depends on CPU_SUP_AMD && 64BIT + menuconfig PROCESSOR_SELECT bool "Supported processor vendors" if EXPERT help @@ -431,6 +435,7 @@ config CPU_SUP_CYRIX_32 config CPU_SUP_AMD default y bool "Support AMD processors" if PROCESSOR_SELECT + select X86_BROADCAST_TLB_FLUSH help This enables detection, tunings and quirks for AMD processors diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 17b6590748c0..f9b832e971c5 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -338,6 +338,7 @@ #define X86_FEATURE_CLZERO (13*32+ 0) /* "clzero" CLZERO instruction */ #define X86_FEATURE_IRPERF (13*32+ 1) /* "irperf" Instructions Retired Count */ #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* "xsaveerptr" Always save/restore FP error pointers */ +#define X86_FEATURE_INVLPGB (13*32+ 3) /* INVLPGB and TLBSYNC instruction supported. */ #define X86_FEATURE_RDPRU (13*32+ 4) /* "rdpru" Read processor register at user level */ #define X86_FEATURE_WBNOINVD (13*32+ 9) /* "wbnoinvd" WBNOINVD instruction */ #define X86_FEATURE_AMD_IBPB (13*32+12) /* Indirect Branch Prediction Barrier */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 02fc2aa06e9e..8fe3b2dda507 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -183,6 +183,13 @@ static inline void cr4_init_shadow(void) extern unsigned long mmu_cr4_features; extern u32 *trampoline_cr4_features; +/* How many pages can we invalidate with one INVLPGB. */ +#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH +extern u16 invlpgb_count_max; +#else +#define invlpgb_count_max 1 +#endif + extern void initialize_tlbstate_and_flush(void); /* diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 79d2e17f6582..bcf73775b4f8 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -29,6 +29,8 @@ #include "cpu.h" +u16 invlpgb_count_max __ro_after_init; + static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) { u32 gprs[8] = { 0 }; @@ -1135,6 +1137,12 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) tlb_lli_2m[ENTRIES] = eax & mask; tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; + + /* Max number of pages INVLPGB can invalidate in one shot */ + if (boot_cpu_has(X86_FEATURE_INVLPGB)) { + cpuid(0x80000008, &eax, &ebx, &ecx, &edx); + invlpgb_count_max = (edx & 0xffff) + 1; + } } static const struct cpu_dev amd_cpu_dev = {