From patchwork Thu Feb 13 16:14:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13973612 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F5B5C021A4 for ; Thu, 13 Feb 2025 16:19:30 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id A140D6B0092; Thu, 13 Feb 2025 11:19:29 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 9C3686B0093; Thu, 13 Feb 2025 11:19:29 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 88BF8280001; Thu, 13 Feb 2025 11:19:29 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0015.hostedemail.com [216.40.44.15]) by kanga.kvack.org (Postfix) with ESMTP id 6A2F76B0092 for ; Thu, 13 Feb 2025 11:19:29 -0500 (EST) Received: from smtpin21.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay05.hostedemail.com (Postfix) with ESMTP id 075944B937 for ; Thu, 13 Feb 2025 16:19:29 +0000 (UTC) X-FDA: 83115431658.21.F55F338 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) by imf19.hostedemail.com (Postfix) with ESMTP id 70E901A0016 for ; Thu, 13 Feb 2025 16:19:27 +0000 (UTC) Authentication-Results: imf19.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf19.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1739463567; a=rsa-sha256; cv=none; b=P/w0i1AIGjq22BQaJ3hReSrCj5cRLoid+G0LhXlaBdLPqZeIgV1C53McvakGKkqYY+h/n3 n6YeguQW/g5glRPaqQjo6EKIWOaFV+t6UHx34KnBtuWiL5ZSL6IcY6jUI3szqoR0Ongrhi nBgXcNhQkSgUphC440zQ23nRJ5Yr3Tw= ARC-Authentication-Results: i=1; imf19.hostedemail.com; dkim=none; dmarc=none; spf=pass (imf19.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1739463567; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CjTLpasyu0xYL9bvYHvochm0jwBg9eEfYvB1mH54d3w=; b=U/gl7AVvMRXX89Z3EV3Jy2Mjsw3wj4JCUC+INURsadAtFwRao/vDUJYfbCNlqrfDUi6+ah FnNtzyf7YbDUFp64NizEUNHPYd+NnIJhwYSbyrWOXFx8g2+w1USpAACYktWuefhDI+O8om 7ZFxqMyIolHtlYrcVybCqBLtxxZ5Sks= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tibr7-000000003xx-1CB0; Thu, 13 Feb 2025 11:14:25 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jackmanb@google.com, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Rik van Riel , Manali Shukla Subject: [PATCH v11 10/12] x86/mm: do targeted broadcast flushing from tlbbatch code Date: Thu, 13 Feb 2025 11:14:01 -0500 Message-ID: <20250213161423.449435-11-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250213161423.449435-1-riel@surriel.com> References: <20250213161423.449435-1-riel@surriel.com> MIME-Version: 1.0 X-Rspam-User: X-Rspamd-Queue-Id: 70E901A0016 X-Rspamd-Server: rspam12 X-Stat-Signature: 5gmbc4t8485xh8k7ictw3i5sccihmxzi X-HE-Tag: 1739463567-609261 X-HE-Meta: U2FsdGVkX1+Dfxsr5IPr6BBnOA4vsmpxxFrG0vHStLIm1+fjQyfJ9fCCVF1ZZZCaG0JAZ33ExSPycQO07mY9ZxKwe+dKL5CsZrcxS8X2Vnb5JAbbZZGIElvIyiNazTQ7kaa+PXnIf3VlAeWYTAviAlkePklvdBbNq2HaRSPE0Ajy1OA/uwUQ/f3jEVTmfz8fEdbRx4cZYqHV9udW2uZH3A9NaPzoEu1Z5Y3EFzDgg2JshPD38ILmrJDuSXdx3KiWnDsdvL04zVUY+HUZMyNAmg+0I6ytIryNBj5RPIzxEYj/gzkYGt/8+Ftlz6nUhmI34DY7P1/xhSIueJXz2fvpVysr7+FbifZHPHDeTCmZjG4bkHIAzMqepZvV7l0vRA93uM53s6XgsH5q5JmwmZ6q+T1KQD/aDzLOI4q3UtTi0gaCttVgb96hxZwZ/sAYJvDUQ2AbIJ/ZoCbx4iEF8TwNOdy4b1Ggw5Zy2++glbQoNQylEUZ04KsSSe5cRiAhzz3JLR2xsprHTFjaxyIp77Xpr2j4KHEiqfJAabQ1TlJARkWbHjrRPUEkmSLzvfjYfCm9a/HIBfNC0ToziCFZ2ImeRR7fUXIDWgKEJwedOMUblbvkNTWqh3dIsoJ7rSip4oqeOzsFGVxNvCd9pDQyAop5Nt5hRSTPheC2IAHTzMMijoBv2UjAx60PmfPVL9oz7qShmNwCMB14PNj7yPoDzwskI4ADFX6vprOf/w9+IfkgsIqqIWn3I4eMsj3njgbIpYgOLkOK2ioi5c6unZxcwgRQrl6Zp4WDcVq5esxH/LoPat2GG5xS37jD/PKj+6ba+ne81AcxoULw3PrzzfpcYkgkLBzb/ozX28w876YDBfPcStOsjSTTUSQzz3mCTtNR6hbRaSyzxqWFGJOj9zA6BuOSGNSKrrVlO0+S8uibsPhmZK/l2xrvSnHKYClhV5fH9jVL6cUTpSa0LLere0biFC0 l/S39QcB GDiIm02sLugGBYqHbfiDWYZRNIybHeXpuY9sNQlwyS29+SIzlTb+g4CdU280bT4yfjcJc9yDDkwgYmPOV3kRRN+kVfjvaoJTkFF9+smvnT29lbMNg3weQPk9S3/25Tc/tCT6zG/1l0F7xQ6S3XDcm331J+ecWROXGdXgtTMiK+mpKTiJPPVwxiFgckkWUeEE7PmCqcXYABOBT67+yPkXOcfUZPGLEXA0AagGObj6xBBw+aRwEs8tBkr7TjrM3zDmW2CUPU8t6QbAiv4x4akzA/EicMZGjMFGI7O9wW6dNq0uWz+cYn8EJc/SE/SoMtLhh9L4RTXB96THVu6iZEtAXGdHmB5wwEwcQlmE86WUZuoTXRlK7oXk2KCZzDYkmVAY0inyatQST5iK/3gD7wyieD1QlsV7Tl09FPiiTA4R8d32AehyI1JN6JRORfNGqENchc06XlNdp8b6cG74HvRZm1RHxJAluZrHqmiPsA1TqtlKqc33LkT8iA0lwmVay5JbROVFr2NF1wpuhDtJA+8BBUBMYJPBOvva9+AW0 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Instead of doing a system-wide TLB flush from arch_tlbbatch_flush, queue up asynchronous, targeted flushes from arch_tlbbatch_add_pending. This also allows us to avoid adding the CPUs of processes using broadcast flushing to the batch->cpumask, and will hopefully further reduce TLB flushing from the reclaim and compaction paths. Signed-off-by: Rik van Riel Tested-by: Manali Shukla Tested-by: Brendan Jackman Tested-by: Michael Kelley --- arch/x86/include/asm/invlpgb.h | 20 ++++----- arch/x86/include/asm/tlbflush.h | 19 ++++---- arch/x86/mm/tlb.c | 79 +++++++++++++++++++++++++++++++-- 3 files changed, 96 insertions(+), 22 deletions(-) diff --git a/arch/x86/include/asm/invlpgb.h b/arch/x86/include/asm/invlpgb.h index a1d5dedd5217..43c331507cc0 100644 --- a/arch/x86/include/asm/invlpgb.h +++ b/arch/x86/include/asm/invlpgb.h @@ -31,7 +31,7 @@ static inline void __invlpgb(unsigned long asid, unsigned long pcid, } /* Wait for INVLPGB originated by this CPU to complete. */ -static inline void tlbsync(void) +static inline void __tlbsync(void) { cant_migrate(); /* TLBSYNC: supported in binutils >= 0.36. */ @@ -61,19 +61,19 @@ static inline void invlpgb_flush_user(unsigned long pcid, unsigned long addr) { __invlpgb(0, pcid, addr, 0, 0, INVLPGB_PCID | INVLPGB_VA); - tlbsync(); + __tlbsync(); } -static inline void invlpgb_flush_user_nr_nosync(unsigned long pcid, - unsigned long addr, - u16 nr, - bool pmd_stride) +static inline void __invlpgb_flush_user_nr_nosync(unsigned long pcid, + unsigned long addr, + u16 nr, + bool pmd_stride) { __invlpgb(0, pcid, addr, nr - 1, pmd_stride, INVLPGB_PCID | INVLPGB_VA); } /* Flush all mappings for a given PCID, not including globals. */ -static inline void invlpgb_flush_single_pcid_nosync(unsigned long pcid) +static inline void __invlpgb_flush_single_pcid_nosync(unsigned long pcid) { __invlpgb(0, pcid, 0, 0, 0, INVLPGB_PCID); } @@ -82,11 +82,11 @@ static inline void invlpgb_flush_single_pcid_nosync(unsigned long pcid) static inline void invlpgb_flush_all(void) { __invlpgb(0, 0, 0, 0, 0, INVLPGB_INCLUDE_GLOBAL); - tlbsync(); + __tlbsync(); } /* Flush addr, including globals, for all PCIDs. */ -static inline void invlpgb_flush_addr_nosync(unsigned long addr, u16 nr) +static inline void __invlpgb_flush_addr_nosync(unsigned long addr, u16 nr) { __invlpgb(0, 0, addr, nr - 1, 0, INVLPGB_INCLUDE_GLOBAL); } @@ -95,7 +95,7 @@ static inline void invlpgb_flush_addr_nosync(unsigned long addr, u16 nr) static inline void invlpgb_flush_all_nonglobals(void) { __invlpgb(0, 0, 0, 0, 0, 0); - tlbsync(); + __tlbsync(); } #endif /* _ASM_X86_INVLPGB */ diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 3080cb8d21dc..27ba17603e0b 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -106,6 +106,9 @@ struct tlb_state { * need to be invalidated. */ bool invalidate_other; +#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH + bool need_tlbsync; +#endif #ifdef CONFIG_ADDRESS_MASKING /* @@ -310,6 +313,10 @@ static inline void broadcast_tlb_flush(struct flush_tlb_info *info) static inline void consider_global_asid(struct mm_struct *mm) { } + +static inline void tlbsync(void) +{ +} #endif #ifdef CONFIG_PARAVIRT @@ -359,21 +366,15 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm) return atomic64_inc_return(&mm->context.tlb_gen); } -static inline void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, - struct mm_struct *mm, - unsigned long uaddr) -{ - inc_mm_tlb_gen(mm); - cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm)); - mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL); -} - static inline void arch_flush_tlb_batched_pending(struct mm_struct *mm) { flush_tlb_mm(mm); } extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch); +extern void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, + struct mm_struct *mm, + unsigned long uaddr); static inline bool pte_flags_need_flush(unsigned long oldflags, unsigned long newflags, diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 0ce0b71a5378..8880bc7456ed 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -492,6 +492,37 @@ static void finish_asid_transition(struct flush_tlb_info *info) WRITE_ONCE(mm->context.asid_transition, false); } +static inline void tlbsync(void) +{ + if (!this_cpu_read(cpu_tlbstate.need_tlbsync)) + return; + __tlbsync(); + this_cpu_write(cpu_tlbstate.need_tlbsync, false); +} + +static inline void invlpgb_flush_user_nr_nosync(unsigned long pcid, + unsigned long addr, + u16 nr, bool pmd_stride) +{ + __invlpgb_flush_user_nr_nosync(pcid, addr, nr, pmd_stride); + if (!this_cpu_read(cpu_tlbstate.need_tlbsync)) + this_cpu_write(cpu_tlbstate.need_tlbsync, true); +} + +static inline void invlpgb_flush_single_pcid_nosync(unsigned long pcid) +{ + __invlpgb_flush_single_pcid_nosync(pcid); + if (!this_cpu_read(cpu_tlbstate.need_tlbsync)) + this_cpu_write(cpu_tlbstate.need_tlbsync, true); +} + +static inline void invlpgb_flush_addr_nosync(unsigned long addr, u16 nr) +{ + __invlpgb_flush_addr_nosync(addr, nr); + if (!this_cpu_read(cpu_tlbstate.need_tlbsync)) + this_cpu_write(cpu_tlbstate.need_tlbsync, true); +} + static void broadcast_tlb_flush(struct flush_tlb_info *info) { bool pmd = info->stride_shift == PMD_SHIFT; @@ -791,6 +822,8 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, if (IS_ENABLED(CONFIG_PROVE_LOCKING)) WARN_ON_ONCE(!irqs_disabled()); + tlbsync(); + /* * Verify that CR3 is what we think it is. This will catch * hypothetical buggy code that directly switches to swapper_pg_dir @@ -970,6 +1003,8 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, */ void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) { + tlbsync(); + if (this_cpu_read(cpu_tlbstate.loaded_mm) == &init_mm) return; @@ -1633,9 +1668,7 @@ void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) * a local TLB flush is needed. Optimize this use-case by calling * flush_tlb_func_local() directly in this case. */ - if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) { - invlpgb_flush_all_nonglobals(); - } else if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) { + if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) { flush_tlb_multi(&batch->cpumask, info); } else if (cpumask_test_cpu(cpu, &batch->cpumask)) { lockdep_assert_irqs_enabled(); @@ -1644,12 +1677,52 @@ void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) local_irq_enable(); } + /* + * If we issued (asynchronous) INVLPGB flushes, wait for them here. + * The cpumask above contains only CPUs that were running tasks + * not using broadcast TLB flushing. + */ + tlbsync(); + cpumask_clear(&batch->cpumask); put_flush_tlb_info(); put_cpu(); } +void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch, + struct mm_struct *mm, + unsigned long uaddr) +{ + u16 asid = mm_global_asid(mm); + + if (asid) { + invlpgb_flush_user_nr_nosync(kern_pcid(asid), uaddr, 1, false); + /* Do any CPUs supporting INVLPGB need PTI? */ + if (static_cpu_has(X86_FEATURE_PTI)) + invlpgb_flush_user_nr_nosync(user_pcid(asid), uaddr, 1, false); + + /* + * Some CPUs might still be using a local ASID for this + * process, and require IPIs, while others are using the + * global ASID. + * + * In this corner case we need to do both the broadcast + * TLB invalidation, and send IPIs. The IPIs will help + * stragglers transition to the broadcast ASID. + */ + if (in_asid_transition(mm)) + asid = 0; + } + + if (!asid) { + inc_mm_tlb_gen(mm); + cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm)); + } + + mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL); +} + /* * Blindly accessing user memory from NMI context can be dangerous * if we're in the middle of switching the current user task or