From patchwork Fri Feb 21 00:53:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rik van Riel X-Patchwork-Id: 13984685 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCD2FC021B2 for ; Fri, 21 Feb 2025 00:55:37 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 1BE27280011; Thu, 20 Feb 2025 19:55:27 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 1471A28000B; Thu, 20 Feb 2025 19:55:27 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id F00E2280011; Thu, 20 Feb 2025 19:55:26 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0010.hostedemail.com [216.40.44.10]) by kanga.kvack.org (Postfix) with ESMTP id C8E1028000B for ; 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b=qNIDO74wQsGJTVsKqc8uwZmmCOk4r6dlYw/KCg2862yL4R5gxlxRW/nZ/k2pQjbnBfj+en TKhOWeF45534m7/nQEerJ6UYj2zQF8j/dN8rVjvFYpMqfVCZGzpcTKb5aMNecAuJwiTVH4 gqkpKPGklGhuiaMk5YeNbLOflZNfTvY= ARC-Authentication-Results: i=1; imf10.hostedemail.com; dkim=none; spf=pass (imf10.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com; dmarc=none ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1740099324; a=rsa-sha256; cv=none; b=dBXc11rsjdgEkln1fr03NXncm5N/Oa6KQXa/VvPauY+eYemXf4gAfVJJqvTiwevHOzIgYy xdWwHmCcfRh/uskKiKFvliY78ADb+DFICH9iTnQSZFkoG015eeRhpYfmGqs4af+kbVnhiZ p4roUYFh9R4ldLGwrkP5oH3yh7/eGPg= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tlHIZ-000000003Qf-1Wgi; Thu, 20 Feb 2025 19:53:47 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jackmanb@google.com, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Manali.Shukla@amd.com, Rik van Riel Subject: [PATCH v12 10/16] x86/mm: global ASID context switch & TLB flush handling Date: Thu, 20 Feb 2025 19:53:09 -0500 Message-ID: <20250221005345.2156760-11-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250221005345.2156760-1-riel@surriel.com> References: <20250221005345.2156760-1-riel@surriel.com> MIME-Version: 1.0 X-Rspamd-Queue-Id: B7115C000C X-Stat-Signature: ki795hfzsbswwy9ipw8sdrkyuchrbsfn X-Rspam-User: X-Rspamd-Server: rspam01 X-HE-Tag: 1740099324-741304 X-HE-Meta: U2FsdGVkX19clNJZVs/aMQ5esILtyd7cq4mUR4JqXBC6kcSIdnDuEhZ/cF0ICO21lYtMC6XQIBRGWJQgee+67jGcvAF3NJ29DCSxeAI2xJknopSoMdsTANYttIXA3WTtn4knNBLH2y65B1C0oRiZR33r7FNhAC8h3onkVIJC/2dg1+w+HMldV+w+NeFtCoDme+3bXK1lFXwUjXso5xvPEPO1Nw+V9QsOhs7KZTj7jGMUlXHmc0w/mtrQr/nUsbad5gOhYvv82CNw0Mx6vS+zr+LXibPKSZeX51T6r0Rdm5EnIUgznIljA1AqgZKjUzSDn9RnbxBQ0WKu9sAUqnsUVqmLAaq/a3SoicU8RgGtXDM3xKMGUPMQo7kf+/XdQJUkut6snUIf0eLUl9k6o9xZR7UJUDv6kJtwBXLpZHm77lvHvr2+2UBBGQJcAa2HXQBRh6NhwzvPfCV55h2ZVr7q9P5ZPFamaEFsTTAs0/2y7OgIjRn0yPKdjB7z/Vvx6aHhrv4x7Q+nJMMyrFfKxUEkC/fdZW5YHTn0TLM6rtuqaANEdDz7d2FUlO0vp/9efG1RnGDyf8tBBpv89TECpG2yatwDNRS9TNWs+Os57zZyhyKS0ImVSvAtpfrWlhruL91wWOUpweGGPjM5AyPemwHYBgB0lMuTIYxC5w/VxX3MGX1z3SazBuZNEi5jPIzB4i80BdjLojHI/URJxtq+WsvLZPHoTGZdrsnv5lNCIkIqM++D5F/kwGwJZP1LbQjUDFDQ4NIMNSCgji2qFHbihIo8Wo8pCuRtiq3+fYc0ZSeKFDD7FP4s8dOv4YatzLHHpP7dG6qkT6TEfgQ6+500DnurPIP9rv9DkEJZghZENKSFySwT0BVMjVq1GxXwd5NpM7LXTPRK+bzZlAoVwqPoocGBJySf+y6AGb9j36ssLowp5DvemLrh9MbbJ929cOwM2w25z3gBrow3g3a6QJuR+lV 4BMubmlk Ma46u4Q79prMF+PbiEU+jQew5IU7mv1dX7JYhGe7hhP3SPL1/7BgqsKdF21odKOCDNUx4V+yxKM4H5QNFHpFRPQ6NcTCCswdLXJ3McjoCYETLKIfZVxXD4B1Sz+SmNLYAEqyLyvCyl7Q6k76NT6Z84k00un/dpexOAXxrscL0LM/TJN1l9682BEqaO48BFf3jZeOT5j87htDVuG6huhjIqY/rUTVHTH0AfBHlXiCRpnSuoEtkTeK5EGQlYZyEmkARlCC1VlTZI4hPz3SPf1BFPdBt0hZGnUOqfGlgDTOePzkt5JiKY0GYb2jx4nszkpwtBwO0gUP9dCBe5ElJzf2Ty0N/7ITiwVLZLkqV9Gq5HbdGcax0bg6wynTGEamqc369gntF X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Context switch and TLB flush support for processes that use a global ASID & PCID across all CPUs. At both context switch time and TLB flush time, we need to check whether a task is switching to a global ASID, and reload the TLB with the new ASID as appropriate. In both code paths, we also short-circuit the TLB flush if we are using a global ASID, because the global ASIDs are always kept up to date across CPUs, even while the process is not running on a CPU. Signed-off-by: Rik van Riel --- arch/x86/include/asm/tlbflush.h | 13 ++++++ arch/x86/mm/tlb.c | 77 ++++++++++++++++++++++++++++++--- 2 files changed, 83 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h index 83f1da2f1e4a..f1f82571249b 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -240,6 +240,19 @@ static inline bool is_dyn_asid(u16 asid) return asid < TLB_NR_DYN_ASIDS; } +static inline bool is_global_asid(u16 asid) +{ + return !is_dyn_asid(asid); +} + +static inline bool in_asid_transition(struct mm_struct *mm) +{ + if (!cpu_feature_enabled(X86_FEATURE_INVLPGB)) + return false; + + return mm && READ_ONCE(mm->context.asid_transition); +} + #ifdef CONFIG_X86_BROADCAST_TLB_FLUSH static inline u16 mm_global_asid(struct mm_struct *mm) { diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 405630479b90..d8a04e398615 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -227,6 +227,20 @@ static void choose_new_asid(struct mm_struct *next, u64 next_tlb_gen, return; } + /* + * TLB consistency for global ASIDs is maintained with hardware assisted + * remote TLB flushing. Global ASIDs are always up to date. + */ + if (static_cpu_has(X86_FEATURE_INVLPGB)) { + u16 global_asid = mm_global_asid(next); + + if (global_asid) { + *new_asid = global_asid; + *need_flush = false; + return; + } + } + if (this_cpu_read(cpu_tlbstate.invalidate_other)) clear_asid_other(); @@ -389,6 +403,23 @@ void destroy_context_free_global_asid(struct mm_struct *mm) global_asid_available++; } +/* + * Is the mm transitioning from a CPU-local ASID to a global ASID? + */ +static bool needs_global_asid_reload(struct mm_struct *next, u16 prev_asid) +{ + u16 global_asid = mm_global_asid(next); + + if (!static_cpu_has(X86_FEATURE_INVLPGB)) + return false; + + /* Process is transitioning to a global ASID */ + if (global_asid && prev_asid != global_asid) + return true; + + return false; +} + /* * Given an ASID, flush the corresponding user ASID. We can delay this * until the next time we switch to it. @@ -694,7 +725,8 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, */ if (prev == next) { /* Not actually switching mm's */ - VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) != + VM_WARN_ON(is_dyn_asid(prev_asid) && + this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) != next->context.ctx_id); /* @@ -711,6 +743,20 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, !cpumask_test_cpu(cpu, mm_cpumask(next)))) cpumask_set_cpu(cpu, mm_cpumask(next)); + /* Check if the current mm is transitioning to a global ASID */ + if (needs_global_asid_reload(next, prev_asid)) { + next_tlb_gen = atomic64_read(&next->context.tlb_gen); + choose_new_asid(next, next_tlb_gen, &new_asid, &need_flush); + goto reload_tlb; + } + + /* + * Broadcast TLB invalidation keeps this PCID up to date + * all the time. + */ + if (is_global_asid(prev_asid)) + return; + /* * If the CPU is not in lazy TLB mode, we are just switching * from one thread in a process to another thread in the same @@ -744,6 +790,13 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, */ cond_mitigation(tsk); + /* + * Let nmi_uaccess_okay() and finish_asid_transition() + * know that we're changing CR3. + */ + this_cpu_write(cpu_tlbstate.loaded_mm, LOADED_MM_SWITCHING); + barrier(); + /* * Leave this CPU in prev's mm_cpumask. Atomic writes to * mm_cpumask can be expensive under contention. The CPU @@ -758,14 +811,12 @@ void switch_mm_irqs_off(struct mm_struct *unused, struct mm_struct *next, next_tlb_gen = atomic64_read(&next->context.tlb_gen); choose_new_asid(next, next_tlb_gen, &new_asid, &need_flush); - - /* Let nmi_uaccess_okay() know that we're changing CR3. */ - this_cpu_write(cpu_tlbstate.loaded_mm, LOADED_MM_SWITCHING); - barrier(); } +reload_tlb: new_lam = mm_lam_cr3_mask(next); if (need_flush) { + VM_WARN_ON_ONCE(is_global_asid(new_asid)); this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id); this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen); load_new_mm_cr3(next->pgd, new_asid, new_lam, true); @@ -884,7 +935,7 @@ static void flush_tlb_func(void *info) const struct flush_tlb_info *f = info; struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm); u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid); - u64 local_tlb_gen = this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen); + u64 local_tlb_gen; bool local = smp_processor_id() == f->initiating_cpu; unsigned long nr_invalidate = 0; u64 mm_tlb_gen; @@ -907,6 +958,16 @@ static void flush_tlb_func(void *info) if (unlikely(loaded_mm == &init_mm)) return; + /* Reload the ASID if transitioning into or out of a global ASID */ + if (needs_global_asid_reload(loaded_mm, loaded_mm_asid)) { + switch_mm_irqs_off(NULL, loaded_mm, NULL); + loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid); + } + + /* Broadcast ASIDs are always kept up to date with INVLPGB. */ + if (is_global_asid(loaded_mm_asid)) + return; + VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].ctx_id) != loaded_mm->context.ctx_id); @@ -924,6 +985,8 @@ static void flush_tlb_func(void *info) return; } + local_tlb_gen = this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen); + if (unlikely(f->new_tlb_gen != TLB_GENERATION_INVALID && f->new_tlb_gen <= local_tlb_gen)) { /* @@ -1091,7 +1154,7 @@ STATIC_NOPV void native_flush_tlb_multi(const struct cpumask *cpumask, * up on the new contents of what used to be page tables, while * doing a speculative memory access. */ - if (info->freed_tables) + if (info->freed_tables || in_asid_transition(info->mm)) on_each_cpu_mask(cpumask, flush_tlb_func, (void *)info, true); else on_each_cpu_cond_mask(should_flush_tlb, flush_tlb_func,