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Fri, 14 Mar 2025 14:40:06 -0700 (PDT) From: Deepak Gupta Date: Fri, 14 Mar 2025 14:39:34 -0700 Subject: [PATCH v12 15/28] riscv/traps: Introduce software check exception MIME-Version: 1.0 Message-Id: <20250314-v5_user_cfi_series-v12-15-e51202b53138@rivosinc.com> References: <20250314-v5_user_cfi_series-v12-0-e51202b53138@rivosinc.com> In-Reply-To: <20250314-v5_user_cfi_series-v12-0-e51202b53138@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, Zong Li , Deepak Gupta X-Mailer: b4 0.14.0 X-Rspam-User: X-Rspamd-Server: rspam11 X-Rspamd-Queue-Id: 66FC1140004 X-Stat-Signature: iqfw45fjsyq93eybqk5ifqcnhzjwe674 X-HE-Tag: 1741988407-590171 X-HE-Meta: U2FsdGVkX1/GXx3yoCoabsSsfcqtuWRgFCjyQ68TNJCH+L1X5ObVnA6V7q75vkACxLwVB1gHz6jITegmt97phP61pzBcHZuYMZZjtnUiNDTWPRcotC+Y2avDw5iJgJbcPvtSaadgj01B+7Y8JDhFtWRga5NWXj4kGJN0FsG1NGE3cwB8EnDEsAumYQ2K6gGKdG/kh3ZNmqn01H/Edq2zyTOis6ySteaJ5TspHhMthnbGkQLIhcmgPTH95pEHcDpwJblZLZI/3IpdvIxZvNXIyRzN9W4EGtNx5DxxDf7SPzn/oVW88fdfrWtphO1JR6B3lIb/7xDWiw3I0eUhMWN5r3lYz5YcTHZ9CAqJhNyOs+R2xYt80Fg+v5I3lIfk359UIjKO4+hC9CUyK+1TaExPIVs/aPrUo/OMihGyDI9ULRUIN3U6W0dV/dfL/8nnYXxwuEiLdEDaBq+Aow0V5owy1285AKwICRisu4ggnCi61w50SBRbH+cnlE96van1Aw2nkatQuhMLAVB9feJ/9RqMvtZtGUJh9hXxb1vLHcZr0Axftyc/41NgCIjDYKmXNzIiCxyO7tiAwVhO1We+mwBtkEbBg9FOrhOqhUvXAR3hOa6t5GzRpMw7SVBI9XCr9LR75v+yaTAd7aICiPsiDy+9tbYWKCH142bkoQlDgA0pA1dtCz0cYYqqZ4N0f0rd2CbYagOZPA/0Obu0QOK0/5toBD/niegYiZb3D17FOYFvLQMjp0lFeP/st4vDq3cU3NQhIpXOU12ZboTHoTso1QipDwzxQuTfddHke86OFCn3PdgAVgaOMxmmCGOFi9BgFTzaNTuOsy/moW7PGgczRj9k04KOocBxplQDCSrrnvPRtwK7MpRKlEOq+ugPOAdHdMlMGV+a4CPpv8cYQSjY3mqLsv24puF+elkBqCAq3fvz/Pa438Z85e7daIgtfqe1vPyhh4POiv6GAWQe8OvXyiI qfiRLzxp fKBSRk8P8glLO1hKP76TyV5iDtRtDsB0V0TseIkrdnHCqrzOaWgWwVBvF80ZGf1NXPozyRH0KlCg/ZvVpRTfLhrlxgeqQoLLG4N+GWMntEedrGHYLC9TqYug0zua1+wDV9f0yXgs9zCv/L58lz2X3FiQHGlhTLeHRlbq6ELYpZjGI46T846QHgBaDZ69PzGAimgghYmxnhltCi4/3MCNKA58dkGhE6hNOeyeqWrFjtLqhB+8z1Uz+0/AaA/qrWYYD70w2BbE2l1Fa8MeMsO2h1fDliMIfvHNoegKgKWPaxXXTs4/nKChsug7dq4pcWpu99ChZp2DzxY5hD9YgBIq6XJi4Ha0yE5k+9Ef1WPTbO6gmIxKlQk58BtLsOMulOvadjv4NEVX9OVu6qt2UWibbGYF3iG9DGDVsTtNru94tbsyf1PYas+UYdd84EcvIvKb1Vt0riUMUhVgdAVndHF7T1hQW8I5bNYClTW0k437xnJhbNK4esWdzrUHQHCI4ZmQyTihDDSPJU4ugdpE= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: zicfiss / zicfilp introduces a new exception to priv isa `software check exception` with cause code = 18. This patch implements software check exception. Additionally it implements a cfi violation handler which checks for code in xtval. If xtval=2, it means that sw check exception happened because of an indirect branch not landing on 4 byte aligned PC or not landing on `lpad` instruction or label value embedded in `lpad` not matching label value setup in `x7`. If xtval=3, it means that sw check exception happened because of mismatch between link register (x1 or x5) and top of shadow stack (on execution of `sspopchk`). In case of cfi violation, SIGSEGV is raised with code=SEGV_CPERR. SEGV_CPERR was introduced by x86 shadow stack patches. Reviewed-by: Zong Li Signed-off-by: Deepak Gupta --- arch/riscv/include/asm/asm-prototypes.h | 1 + arch/riscv/include/asm/entry-common.h | 2 ++ arch/riscv/kernel/entry.S | 3 +++ arch/riscv/kernel/traps.c | 43 +++++++++++++++++++++++++++++++++ 4 files changed, 49 insertions(+) diff --git a/arch/riscv/include/asm/asm-prototypes.h b/arch/riscv/include/asm/asm-prototypes.h index cd627ec289f1..5a27cefd7805 100644 --- a/arch/riscv/include/asm/asm-prototypes.h +++ b/arch/riscv/include/asm/asm-prototypes.h @@ -51,6 +51,7 @@ DECLARE_DO_ERROR_INFO(do_trap_ecall_u); DECLARE_DO_ERROR_INFO(do_trap_ecall_s); DECLARE_DO_ERROR_INFO(do_trap_ecall_m); DECLARE_DO_ERROR_INFO(do_trap_break); +DECLARE_DO_ERROR_INFO(do_trap_software_check); asmlinkage void handle_bad_stack(struct pt_regs *regs); asmlinkage void do_page_fault(struct pt_regs *regs); diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm/entry-common.h index b28ccc6cdeea..34ed149af5d1 100644 --- a/arch/riscv/include/asm/entry-common.h +++ b/arch/riscv/include/asm/entry-common.h @@ -40,4 +40,6 @@ static inline int handle_misaligned_store(struct pt_regs *regs) } #endif +bool handle_user_cfi_violation(struct pt_regs *regs); + #endif /* _ASM_RISCV_ENTRY_COMMON_H */ diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 00494b54ff4a..9c00cac3f6f2 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -472,6 +472,9 @@ SYM_DATA_START_LOCAL(excp_vect_table) RISCV_PTR do_page_fault /* load page fault */ RISCV_PTR do_trap_unknown RISCV_PTR do_page_fault /* store page fault */ + RISCV_PTR do_trap_unknown /* cause=16 */ + RISCV_PTR do_trap_unknown /* cause=17 */ + RISCV_PTR do_trap_software_check /* cause=18 is sw check exception */ SYM_DATA_END_LABEL(excp_vect_table, SYM_L_LOCAL, excp_vect_table_end) #ifndef CONFIG_MMU diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 8ff8e8b36524..3f7709f4595a 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -354,6 +354,49 @@ void do_trap_ecall_u(struct pt_regs *regs) } +#define CFI_TVAL_FCFI_CODE 2 +#define CFI_TVAL_BCFI_CODE 3 +/* handle cfi violations */ +bool handle_user_cfi_violation(struct pt_regs *regs) +{ + bool ret = false; + unsigned long tval = csr_read(CSR_TVAL); + + if ((tval == CFI_TVAL_FCFI_CODE && cpu_supports_indirect_br_lp_instr()) || + (tval == CFI_TVAL_BCFI_CODE && cpu_supports_shadow_stack())) { + do_trap_error(regs, SIGSEGV, SEGV_CPERR, regs->epc, + "Oops - control flow violation"); + ret = true; + } + + return ret; +} + +/* + * software check exception is defined with risc-v cfi spec. Software check + * exception is raised when:- + * a) An indirect branch doesn't land on 4 byte aligned PC or `lpad` + * instruction or `label` value programmed in `lpad` instr doesn't + * match with value setup in `x7`. reported code in `xtval` is 2. + * b) `sspopchk` instruction finds a mismatch between top of shadow stack (ssp) + * and x1/x5. reported code in `xtval` is 3. + */ +asmlinkage __visible __trap_section void do_trap_software_check(struct pt_regs *regs) +{ + if (user_mode(regs)) { + irqentry_enter_from_user_mode(regs); + + /* not a cfi violation, then merge into flow of unknown trap handler */ + if (!handle_user_cfi_violation(regs)) + do_trap_unknown(regs); + + irqentry_exit_to_user_mode(regs); + } else { + /* sw check exception coming from kernel is a bug in kernel */ + die(regs, "Kernel BUG"); + } +} + #ifdef CONFIG_MMU asmlinkage __visible noinstr void do_page_fault(struct pt_regs *regs) {