From patchwork Fri Aug 10 18:13:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aapo Vienamo X-Patchwork-Id: 10563065 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 042B013BB for ; Fri, 10 Aug 2018 18:14:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E18082BE90 for ; Fri, 10 Aug 2018 18:14:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D4AA52BE96; Fri, 10 Aug 2018 18:14:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7FC602BE90 for ; Fri, 10 Aug 2018 18:14:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728630AbeHJUpI (ORCPT ); Fri, 10 Aug 2018 16:45:08 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:11854 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728001AbeHJUpI (ORCPT ); Fri, 10 Aug 2018 16:45:08 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Fri, 10 Aug 2018 11:13:57 -0700 Received: from HQMAIL104.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 10 Aug 2018 11:14:05 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 10 Aug 2018 11:14:05 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Fri, 10 Aug 2018 18:14:11 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Fri, 10 Aug 2018 18:14:11 +0000 Received: from dhcp-10-21-25-168.Nvidia.com (Not Verified[10.21.25.201]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 10 Aug 2018 11:14:11 -0700 From: Aapo Vienamo To: Ulf Hansson , Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , Adrian Hunter , Mikko Perttunen CC: , , , , Aapo Vienamo Subject: [PATCH v2 0/8] Tegra SDHCI support HS400 on Tegra210 and Tegra186 Date: Fri, 10 Aug 2018 21:13:57 +0300 Message-ID: <1533924845-1466-1-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi all, This series implements support for HS400 signaling on Tegra210 and Tegra186. This includes programming the DQS trimmer values, implementing enhanced strobe and HS400 delay line calibration. This series depends on the "Tegra SDHCI add support for HS200 and UHS signaling" series. Changelog: v2: - Document in dt-bindings which controllers support HS400 - Use val instead of reg in tegra_sdhci_set_dqs_trim() - Change "dt" to "DT" in "mmc: tegra: Parse and program DQS trim value" commit message - Add spaces around << in tegra_sdhci_set_dqs_trim() - Make the "mmc: tegra: Implement HS400 enhanced strobe" commit message more detailed - Remove a debug print from tegra_sdhci_hs400_enhanced_strobe() - Add blank lines around if-else-block in tegra_sdhci_hs400_enhanced_strobe() - Use val instead of reg in tegra_sdhci_hs400_enhanced_strobe() - Make commit message of "mmc: tegra: Implement HS400 delay line calibration" more detailed Aapo Vienamo (8): dt-bindings: mmc: Add DQS trim value to Tegra SDHCI mmc: tegra: Parse and program DQS trim value mmc: tegra: Implement HS400 enhanced strobe mmc: tegra: Implement HS400 delay line calibration arm64: dts: tegra186: Add SDMMC4 DQS trim value arm64: dts: tegra210: Add SDMMC4 DQS trim value arm64: dts: tegra186: Enable HS400 arm64: dts: tegra210: Enable HS400 .../bindings/mmc/nvidia,tegra20-sdhci.txt | 4 ++ arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 + arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 + drivers/mmc/host/sdhci-tegra.c | 84 +++++++++++++++++++++- 4 files changed, 89 insertions(+), 3 deletions(-) Acked-by: Thierry Reding