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Tue, 19 Nov 2019 22:47:42 -0800 Received: from xsj-pvapsmtp01 (maildrop.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id xAK6la1t001801; Tue, 19 Nov 2019 22:47:37 -0800 Received: from [172.23.64.106] (helo=xhdvnc125.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iXJm4-00048z-KB; Tue, 19 Nov 2019 22:47:36 -0800 Received: by xhdvnc125.xilinx.com (Postfix, from userid 16987) id D1B9A12127B; Wed, 20 Nov 2019 12:17:35 +0530 (IST) From: Manish Narani To: ulf.hansson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, adrian.hunter@intel.com, michal.simek@xilinx.com, jolly.shah@xilinx.com, rajan.vaja@xilinx.com, nava.manne@xilinx.com, mdf@kernel.org, manish.narani@xilinx.com Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, git@xilinx.com Subject: [PATCH v6 0/8] Arasan SDHCI enhancements and ZynqMP Tap Delays Handling Date: Wed, 20 Nov 2019 12:17:21 +0530 Message-Id: <1574232449-13570-1-git-send-email-manish.narani@xilinx.com> X-Mailer: git-send-email 2.1.1 X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(136003)(346002)(376002)(39860400002)(396003)(199004)(189003)(106002)(14444005)(186003)(44832011)(26005)(336012)(47776003)(36386004)(4326008)(6666004)(356004)(36756003)(126002)(107886003)(486006)(2616005)(6266002)(51416003)(48376002)(81156014)(81166006)(476003)(8676002)(426003)(5660300002)(478600001)(8936002)(50226002)(305945005)(2906002)(316002)(16586007)(42186006)(70206006)(70586007)(50466002)(103686004)(921003)(1121003);DIR:OUT;SFP:1101;SCL:1;SRVR:MN2PR02MB6687;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;A:1;MX:1; MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5b23c3b4-a715-4da2-dae9-08d76d858e51 X-MS-TrafficTypeDiagnostic: MN2PR02MB6687: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:6790; X-Forefront-PRVS: 02272225C5 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 9Q4r4i8EQ6JMs1lmmu7Jqz6E1G2TVBuF90GxuANexQDXB7nBK44COqV+4MWQKxHmS2o+cF09Vyg9AMV5yQIYZ3sDdisvLAyrmi0RqdnuBMHK4/Dj3ttH2hz23KKfCUmnmKKuddX2RFSji/Nldd9hvnyjLMUEIkRig0paeJSnbHbyzqb6a5EeRi38hrWT1o0gqe+lZWgNEuBPHeoYdrQCoY5sl3R1HjF+4n15XIRy2Vbjh/n9HemLCHsuE20D4hOdcSkRLpnmvUehg6nddf0YQ39mm+52hPi/jWQWDd7gaMLYLbdluaqYs1LtXYqPyjDqSZcegz/0OdpesrER9DaBugAn1BY/NHI1h6lFw5j+5JAF6BT2P8i79L+pB4chnPpCIWM4bDe5sWfbw8R2hrzrDBP6eho2o8Loqn9HZULjeM0sqwcriNwWZRrqiWyY9U3U X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Nov 2019 06:47:48.0270 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5b23c3b4-a715-4da2-dae9-08d76d858e51 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR02MB6687 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org This patch series does the following: - Reorganize the Clock Handling in Arasan SD driver - Adds new sampling clock in Arasan SD driver - Adds support to set Clock Delays in SD Arasan Driver - Add SDIO Tap Delay handling in ZynqMP firmware driver - Add support for ZynqMP Tap Delays setting in Arasan SD driver Changes in v2: - Replaced the deprecated calls to clock framework APIs - Added support for dev_clk_get() call to work for SD card clock - Separated the clock data struct - Fragmented the patch series in smaller patches to make it more readable Changes in v3: - Reverted "Replaced the deprecated calls to clock framework APIs" - Removed devm_clk_get() call which was added in v2 Changes in v4: - Made the Phase Delay properties Arasan specific Changes in v5: - Made Clock Phase Delay properties common - Moved documentation of them to the common mmc documentation. Changes in v6: - Clubbed all Clk Phase Delay properties' into a pattern Property Manish Narani (8): mmc: sdhci-of-arasan: Separate out clk related data to another structure dt-bindings: mmc: arasan: Update Documentation for the input clock mmc: sdhci-of-arasan: Add sampling clock for a phy to use dt-bindings: mmc: Add optional generic properties for mmc mmc: sdhci-of-arasan: Add support to set clock phase delays for SD firmware: xilinx: Add SDIO Tap Delay nodes dt-bindings: mmc: arasan: Document 'xlnx,zynqmp-8.9a' controller mmc: sdhci-of-arasan: Add support for ZynqMP Platform Tap Delays Setup .../devicetree/bindings/mmc/arasan,sdhci.txt | 25 +- .../bindings/mmc/mmc-controller.yaml | 13 + drivers/mmc/host/sdhci-of-arasan.c | 478 +++++++++++++++++- include/linux/firmware/xlnx-zynqmp.h | 13 +- 4 files changed, 497 insertions(+), 32 deletions(-)