From patchwork Wed Oct 14 03:08:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?V2VuYmluIE1laSAo5qKF5paH5b2sKQ==?= X-Patchwork-Id: 11836719 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A7E5A1592 for ; Wed, 14 Oct 2020 03:08:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7EBF721D7F for ; Wed, 14 Oct 2020 03:08:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="r1mc4EDV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729298AbgJNDI4 (ORCPT ); Tue, 13 Oct 2020 23:08:56 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:40284 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729258AbgJNDI4 (ORCPT ); Tue, 13 Oct 2020 23:08:56 -0400 X-UUID: 7e7f51a598f44e028ec368430013eb28-20201014 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=nEv/nfQEf7Kv7V9kivAP7rJMl1OjvecHjq9vDRJ/g7Q=; b=r1mc4EDVt5a/Z1MV9iIItpFbFqecrZZg+A5jn9jL1qT3nV/rgRIWJ0QL0TTtsad5zkhVzBXY0Lb9eez23ccmA2ZdDzIeSFWLBGxj0XxUcQeESXo+2ZbvcwtLTcw/EzZ+yznVAe0bYMSslErzznYBG6XzuMU8YcU0pIpFQKFi7T8=; X-UUID: 7e7f51a598f44e028ec368430013eb28-20201014 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1734856836; Wed, 14 Oct 2020 11:08:50 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 14 Oct 2020 11:08:47 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 14 Oct 2020 11:08:47 +0800 From: Wenbin Mei To: Ulf Hansson , Rob Herring CC: Chaotian Jing , Matthias Brugger , , , , , , Subject: [PATCH v7 0/4] Add mmc support for MT8192 SoC Date: Wed, 14 Oct 2020 11:08:42 +0800 Message-ID: <20201014030846.12428-1-wenbin.mei@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Change in v7: 1)add "unevaluatedProperties" in mtk-sd.yaml 2)add Reviewed-by tag Change in v6: 1)use devm_clk_get function for required clocks Change in v5: 1)remove Reviewed-by tag 2)use devm_clk_bulk_get_optional instead of devm_clk_get_optional for bulk clks Change in v4: 1)drop "vmmc" and "vqmmc" desciption in mtk-sd.yaml 2)add vmmq/vqmmc supplies and the pinctrls to required properties 3)change dbg level and exit this function 4)use devm_clk_get_optional instead of devm_clk_get function 5)remove else branch for sys_clk_cg Change in v3: 1)change maintainers name in mtk-sd.yaml 2)change "compatible" properties to enum type and sort it 3)drop these properties: "reg" and "interrupts" 4)add "maxItems" constraints on these properties: "vmmc-supply", "vqmmc-supply", "assigned-clocks", "assigned-clock-parents" 5)add "minimum" and "maximum" constraints on these properties: "mediatek,hs400-cmd-int-delay", "mediatek,latch-ck", "hs400-ds-delay", "mediatek,hs200-cmd-int-delay" Change in v2: Convert mtk-sd to json-schema Wenbin Mei (4): dt-bindings: mmc: Convert mtk-sd to json-schema mmc: dt-bindings: add support for MT8192 SoC arm64: dts: mt8192: add mmc device node mmc: mediatek: Add subsys clock control for MT8192 msdc --- This patch depends on [v4,1/3] arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile [v3,1/9] dt-bindings: ARM: Mediatek: Document bindings for MT8192 BSP [v3,6/9] clk: mediatek: Add dt-bindings for MT8192 clocks [v3,9/9] clk: mediatek: Add MT8192 clock support [v3,1/3] dt-bindings: pinctrl: mt8192: add pinctrl file [v3,2/3] dt-bindings: pinctrl: mt8192: add binding document [v3,3/3] pinctrl: add pinctrl driver on mt8192 [v2,1/4] soc: mediatek: pwrap: use BIT() macro [v2,2/4] soc: mediatek: pwrap: add arbiter capability [v2,3/4] dt-bindings: mediatek: add compatible for MT6873/8192 pwrap [v2,4/4] soc: mediatek: pwrap: add pwrap driver for MT6873/8192 SoCs [2/8] dt-bindings: mfd: Add compatible for the MediaTek MT6359 PMIC [3/8] dt-bindings: regulator: Add document for MT6359 regulator [4/8] mfd: Add support for the MediaTek MT6359 PMIC [5/8] regulator: mt6359: Add support for MT6359 regulator [7/8] regulator: mt6359: Add support for MT6359P regulator [8/8] arm64: dts: mt6359: add PMIC MT6359 related nodes Please also accept this patch together with [1][2][3][4][5] to avoid build and dt binding check error. [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=332621 [2] https://patchwork.kernel.org/project/linux-mediatek/list/?series=342593 [3] https://patchwork.kernel.org/project/linux-mediatek/list/?series=330017 [4] https://patchwork.kernel.org/project/linux-mediatek/list/?series=322937 [5] https://patchwork.kernel.org/project/linux-mediatek/list/?series=323171 --- .../devicetree/bindings/mmc/mtk-sd.txt | 75 -------- .../devicetree/bindings/mmc/mtk-sd.yaml | 176 ++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 89 +++++++++ arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 ++++ drivers/mmc/host/mtk-sd.c | 74 ++++++-- 5 files changed, 355 insertions(+), 93 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mmc/mtk-sd.txt create mode 100644 Documentation/devicetree/bindings/mmc/mtk-sd.yaml -- 2.18.0